On Sat, Dec 11, 2010 at 04:05:11PM +0000, Peter Clifton wrote:
> Well, don't forget to raise the issues here - you might find you get
> some of them fixed for free ;) Fixing issues affecting everyone
> benefits everyone. If they are very complex to fix, sponsoring someone
> with the required know-how to fix them might speed up the process of
> course.
It took me a little longer, but I have bunch of issues I need to
address.
For larger desings it is needed to
automaticly(pseudo-automaticly) connect pins/vias/pads with
polygon they lay in if there is rat to that polygon(or something
else the polygon intersect with). Good example is polygon
connected to GND.
This one will probably need assingment of net to polygons.
I want to write a little work-around. Iam writting action for
selecting net by name. Should work like clicking on net name in
netlist window and then button select. I think that such action
will be usefull in general.
Sometimes, when you place to lines too close, but not that close
in polygon. It will make thin line in the polygon connecting two
part of the polygon. DRC will mark this line as too thin. It
should automaticly erase such lines. Any proposal, how to fix
this?
When you make a via in polygon. Change the clerance to too
small value and add thermal(even full thermal). DRC will mark
this via as having too smal clearance. This seems like bug to
me.
Bigger issues is that when I drag component, lines are dragged
with it. This is fine, but the lines do not respect any
orthogonal/45 deg rules.
I cannot simply unmask part of the board. I know how to do it,
but that is not optimal. Having some Solder mask layer with
polygons clearing solder mask would be neat.
And one question. Is it possible to enable snapping to end of
lines? I know about snapping to pins/pads/vias, but have not
found how to snap to end of line.
This list is just what we came into when trying PCB.
I am definetly not blaming anyone for any of those issuses.
Just letting you know what are my problems.
Martin Kupec
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