On Sunday 16 January 2011, John Griessen wrote: > On 01/15/2011 10:36 PM, al davis wrote: > > Unless I massively missed something, verilog is completely > > procedural. > > Really verilog is all in parallel, not procedural code, > unless you want to put some in with special features that > are trickier to use than everyday verilog. > > The basic statement of verilog is assign, which defines wires > and connectivity of busses of wires and renamings and logical > combinations of wire values... Much like a graphical > schematic. > > Modules also map names in verilog, allowing reuse of subcells > with different names for wires inside them.
You are thinking of the original Verilog, as it was in its first draft from Cadence over 20 years ago. Today, Verilog means a family of languages with common syntax that do just about everything in electronics. There is System Verilog, Verilog-A, Verilog-AMS, .... The insiders refer to the old digital verilog alone as "Verilog-D". If simulation means Spice to you, you are 20 years behind. If Verilog means only digital to you, you are 20 years behind. Are we proud of being 20 years behind? _______________________________________________ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user