On Tuesday 06 April 2004 12:46 pm, John Griessen wrote: > Verilog wires give 0, 1, or X usually, and sometimes they can deal in > drive strengths to yield a weak 1 or weak 0... and I've forgotten if > Z state is a built in, and can't help you with the High Z tristate bus > driver example.
Z is a basic primitive value for Verilog. -- Samuel A. Falvo II
