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src/arch/mips/isa/decoder.isa <http://reviews.m5sim.org/r/748/#comment1800> This is a separate patch then the mips branch prediction. IF you have updates for the same patch, then update it. If you are patching a differen issue, please post a new review for that. This is important for logging of changesets. Also, did you test this through observation of wrong output or through comparing against the ISA spec? src/arch/mips/isa/decoder.isa <http://reviews.m5sim.org/r/748/#comment1799> same as above Why would nmsub add and nmadd subtract? src/cpu/inorder/inorder_dyn_inst.cc <http://reviews.m5sim.org/r/748/#comment1801> separate patch. also, what code in locked_mem.hh requires this? - Korey On 2011-06-21 02:16:53, Deyuan Guo wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.m5sim.org/r/748/ > ----------------------------------------------------------- > > (Updated 2011-06-21 02:16:53) > > > Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and > Nathan Binkert. > > > Summary > ------- > > Make the newly gem5 support mips branch likely instruction again. > Fix 4 files: > src/arch/mips/isa/formats/branch.isa > src/cpu/inorder/inorder_dyn_inst.cc > src/cpu/inorder/resources/branch_predictor.cc > src/cpu/inorder/resources/fetch_seq_unit.cc > > > Diffs > ----- > > src/arch/mips/isa/decoder.isa 00766f5b8177 > src/arch/mips/isa/formats/branch.isa 00766f5b8177 > src/cpu/inorder/inorder_dyn_inst.cc 00766f5b8177 > src/cpu/inorder/resources/branch_predictor.cc 00766f5b8177 > src/cpu/inorder/resources/fetch_seq_unit.cc 00766f5b8177 > > Diff: http://reviews.m5sim.org/r/748/diff > > > Testing > ------- > > Tested. > > > Thanks, > > Deyuan > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
