changeset b1f3dfae06f1 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=b1f3dfae06f1
description:
ISA: Use readBytes/writeBytes for all instruction level memory
operations.
diffstat:
src/arch/alpha/isa/main.isa | 1 +
src/arch/alpha/isa/mem.isa | 18 ++--
src/arch/arm/isa/includes.isa | 1 +
src/arch/arm/isa/templates/mem.isa | 33 ++++----
src/arch/generic/memhelpers.hh | 100 ++++++++++++++++++++++++++
src/arch/mips/isa/formats/mem.isa | 39 +++++-----
src/arch/mips/isa/includes.isa | 1 +
src/arch/power/isa/formats/mem.isa | 14 +-
src/arch/power/isa/includes.isa | 1 +
src/arch/sparc/isa/formats/mem/swap.isa | 11 +-
src/arch/sparc/isa/formats/mem/util.isa | 12 +-
src/arch/sparc/isa/includes.isa | 1 +
src/arch/x86/insts/microldstop.hh | 67 -----------------
src/arch/x86/isa/includes.isa | 1 +
src/arch/x86/isa/microops/ldstop.isa | 12 +-
src/arch/x86/memhelpers.hh | 120 ++++++++++++++++++++++++++++++++
16 files changed, 297 insertions(+), 135 deletions(-)
diffs (truncated from 825 to 300 lines):
diff -r 49e0034e2559 -r b1f3dfae06f1 src/arch/alpha/isa/main.isa
--- a/src/arch/alpha/isa/main.isa Sat Jul 02 22:31:42 2011 -0700
+++ b/src/arch/alpha/isa/main.isa Sat Jul 02 22:34:29 2011 -0700
@@ -73,6 +73,7 @@
#include "arch/alpha/registers.hh"
#include "arch/alpha/regredir.hh"
+#include "arch/generic/memhelpers.hh"
#include "base/cp_annotate.hh"
#include "base/fenv.hh"
#include "config/ss_compatible_fp.hh"
diff -r 49e0034e2559 -r b1f3dfae06f1 src/arch/alpha/isa/mem.isa
--- a/src/arch/alpha/isa/mem.isa Sat Jul 02 22:31:42 2011 -0700
+++ b/src/arch/alpha/isa/mem.isa Sat Jul 02 22:34:29 2011 -0700
@@ -197,7 +197,7 @@
%(ea_code)s;
if (fault == NoFault) {
- fault = xc->read(EA, (uint%(mem_acc_size)d_t&)Mem, memAccessFlags);
+ fault = readMemAtomic(xc, traceData, EA, Mem, memAccessFlags);
%(memacc_code)s;
}
@@ -223,7 +223,7 @@
%(ea_code)s;
if (fault == NoFault) {
- fault = xc->read(EA, (uint%(mem_acc_size)d_t &)Mem,
memAccessFlags);
+ fault = readMemTiming(xc, traceData, EA, Mem, memAccessFlags);
}
return fault;
@@ -241,7 +241,7 @@
%(fp_enable_check)s;
%(op_decl)s;
- Mem = pkt->get<typeof(Mem)>();
+ getMem(pkt, Mem, traceData);
if (fault == NoFault) {
%(memacc_code)s;
@@ -273,8 +273,8 @@
}
if (fault == NoFault) {
- fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
- memAccessFlags, NULL);
+ fault = writeMemAtomic(xc, traceData, Mem, EA,
+ memAccessFlags, NULL);
}
if (fault == NoFault) {
@@ -307,8 +307,8 @@
}
if (fault == NoFault) {
- fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
- memAccessFlags, &write_result);
+ fault = writeMemAtomic(xc, traceData, Mem, EA,
+ memAccessFlags, &write_result);
}
if (fault == NoFault) {
@@ -340,8 +340,8 @@
}
if (fault == NoFault) {
- fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
- memAccessFlags, NULL);
+ fault = writeMemTiming(xc, traceData, Mem, EA,
+ memAccessFlags, NULL);
}
return fault;
diff -r 49e0034e2559 -r b1f3dfae06f1 src/arch/arm/isa/includes.isa
--- a/src/arch/arm/isa/includes.isa Sat Jul 02 22:31:42 2011 -0700
+++ b/src/arch/arm/isa/includes.isa Sat Jul 02 22:34:29 2011 -0700
@@ -80,6 +80,7 @@
#include "arch/arm/faults.hh"
#include "arch/arm/isa_traits.hh"
#include "arch/arm/utility.hh"
+#include "arch/generic/memhelpers.hh"
#include "base/condcodes.hh"
#include "sim/pseudo_inst.hh"
#if defined(linux)
diff -r 49e0034e2559 -r b1f3dfae06f1 src/arch/arm/isa/templates/mem.isa
--- a/src/arch/arm/isa/templates/mem.isa Sat Jul 02 22:31:42 2011 -0700
+++ b/src/arch/arm/isa/templates/mem.isa Sat Jul 02 22:34:29 2011 -0700
@@ -87,8 +87,8 @@
%(preacc_code)s;
if (fault == NoFault) {
- fault = xc->write((uint%(mem_acc_size)d_t&)Mem,
- EA, memAccessFlags, &memData);
+ fault = writeMemAtomic(xc, traceData, Mem, EA, memAccessFlags,
+ &memData);
}
if (fault == NoFault) {
@@ -123,8 +123,8 @@
%(preacc_code)s;
if (fault == NoFault) {
- fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
- memAccessFlags, &memData);
+ fault = writeMemTiming(xc, traceData, Mem, EA, memAccessFlags,
+ &memData);
}
} else {
xc->setPredicate(false);
@@ -147,7 +147,8 @@
if (%(predicate_test)s)
{
// ARM instructions will not have a pkt if the predicate is false
- uint64_t memData = pkt->get<typeof(Mem)>();
+ getMem(pkt, Mem, traceData);
+ uint64_t memData = Mem;
%(postacc_code)s;
@@ -174,7 +175,7 @@
if (%(predicate_test)s)
{
if (fault == NoFault) {
- fault = xc->read(EA, (uint%(mem_acc_size)d_t&)Mem,
memAccessFlags);
+ fault = readMemAtomic(xc, traceData, EA, Mem, memAccessFlags);
%(memacc_code)s;
}
@@ -241,8 +242,8 @@
}
if (fault == NoFault) {
- fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
- memAccessFlags, NULL);
+ fault = writeMemAtomic(xc, traceData, Mem, EA,
+ memAccessFlags, NULL);
}
if (fault == NoFault) {
@@ -314,8 +315,8 @@
uint64_t writeResult;
if (fault == NoFault) {
- fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
- memAccessFlags, &writeResult);
+ fault = writeMemAtomic(xc, traceData, Mem, EA, memAccessFlags,
+ &writeResult);
}
if (fault == NoFault) {
@@ -351,8 +352,8 @@
}
if (fault == NoFault) {
- fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
- memAccessFlags, NULL);
+ fault = writeMemTiming(xc, traceData, Mem, EA, memAccessFlags,
+ NULL);
}
} else {
xc->setPredicate(false);
@@ -380,8 +381,8 @@
}
if (fault == NoFault) {
- fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
- memAccessFlags, NULL);
+ fault = writeMemTiming(xc, traceData, Mem, EA, memAccessFlags,
+ NULL);
}
} else {
xc->setPredicate(false);
@@ -437,7 +438,7 @@
if (%(predicate_test)s)
{
if (fault == NoFault) {
- fault = xc->read(EA, (uint%(mem_acc_size)d_t &)Mem,
memAccessFlags);
+ fault = readMemTiming(xc, traceData, EA, Mem, memAccessFlags);
}
} else {
xc->setPredicate(false);
@@ -489,7 +490,7 @@
if (%(predicate_test)s)
{
// ARM instructions will not have a pkt if the predicate is false
- Mem = pkt->get<typeof(Mem)>();
+ getMem(pkt, Mem, traceData);
if (fault == NoFault) {
%(memacc_code)s;
diff -r 49e0034e2559 -r b1f3dfae06f1 src/arch/generic/memhelpers.hh
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/src/arch/generic/memhelpers.hh Sat Jul 02 22:34:29 2011 -0700
@@ -0,0 +1,100 @@
+/*
+ * Copyright (c) 2011 Google
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#ifndef __ARCH_GENERIC_MEMHELPERS_HH__
+#define __ARCH_GENERIC_MEMHELPERS_HH__
+
+#include "base/types.hh"
+#include "sim/byteswap.hh"
+#include "sim/fault_fwd.hh"
+#include "sim/insttracer.hh"
+
+/// Read from memory in timing mode.
+template <class XC, class MemT>
+Fault
+readMemTiming(XC *xc, Trace::InstRecord *traceData, Addr addr,
+ MemT &mem, unsigned flags)
+{
+ return xc->readBytes(addr, (uint8_t *)&mem, sizeof(MemT), flags);
+}
+
+/// Extract the data returned from a timing mode read.
+template <class MemT>
+void
+getMem(PacketPtr pkt, MemT &mem, Trace::InstRecord *traceData)
+{
+ mem = pkt->get<MemT>();
+ if (traceData)
+ traceData->setData(mem);
+}
+
+/// Read from memory in atomic mode.
+template <class XC, class MemT>
+Fault
+readMemAtomic(XC *xc, Trace::InstRecord *traceData, Addr addr, MemT &mem,
+ unsigned flags)
+{
+ memset(&mem, 0, sizeof(mem));
+ Fault fault = readMemTiming(xc, traceData, addr, mem, flags);
+ if (fault == NoFault) {
+ mem = gtoh(mem);
+ if (traceData)
+ traceData->setData(mem);
+ }
+ return fault;
+}
+
+/// Write to memory in timing mode.
+template <class XC, class MemT>
+Fault
+writeMemTiming(XC *xc, Trace::InstRecord *traceData, MemT mem, Addr addr,
+ unsigned flags, uint64_t *res)
+{
+ if (traceData) {
+ traceData->setData(mem);
+ }
+ mem = TheISA::htog(mem);
+ return xc->writeBytes((uint8_t *)&mem, sizeof(MemT), addr, flags, res);
+}
+
+/// Write to memory in atomic mode.
+template <class XC, class MemT>
+Fault
+writeMemAtomic(XC *xc, Trace::InstRecord *traceData, const MemT &mem,
+ Addr addr, unsigned flags, uint64_t *res)
+{
+ Fault fault = writeMemTiming(xc, traceData, mem, addr, flags, res);
+ if (fault == NoFault && res != NULL) {
+ *res = gtoh((MemT)*res);
+ }
+ return fault;
+}
+
+#endif
diff -r 49e0034e2559 -r b1f3dfae06f1 src/arch/mips/isa/formats/mem.isa
--- a/src/arch/mips/isa/formats/mem.isa Sat Jul 02 22:31:42 2011 -0700
+++ b/src/arch/mips/isa/formats/mem.isa Sat Jul 02 22:34:29 2011 -0700
@@ -216,7 +216,7 @@
%(ea_code)s;
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