changeset 56de1f9320df in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=56de1f9320df
description:
ExecContext: Rename the readBytes/writeBytes functions to readMem and
writeMem.
readBytes and writeBytes had the word "bytes" in their names because
they
accessed blobs of bytes. This distinguished them from the read and write
functions which handled higher level data types. Because those
functions don't
exist any more, this change renames readBytes and writeBytes to more
general
names, readMem and writeMem, which reflect the fact that they are how
you read
and write memory. This also makes their names more consistent with the
register reading/writing functions, although those are still read and
set for
some reason.
diffstat:
src/arch/arm/isa/templates/mem.isa | 12 ++++++------
src/arch/generic/memhelpers.hh | 4 ++--
src/arch/x86/memhelpers.hh | 4 ++--
src/cpu/base_dyn_inst.hh | 14 +++++++-------
src/cpu/exec_context.hh | 6 +++---
src/cpu/inorder/inorder_dyn_inst.cc | 8 ++++----
src/cpu/inorder/inorder_dyn_inst.hh | 6 +++---
src/cpu/simple/atomic.cc | 8 ++++----
src/cpu/simple/atomic.hh | 6 +++---
src/cpu/simple/timing.cc | 8 ++++----
src/cpu/simple/timing.hh | 6 +++---
11 files changed, 41 insertions(+), 41 deletions(-)
diffs (265 lines):
diff -r 530ff1bc8d70 -r 56de1f9320df src/arch/arm/isa/templates/mem.isa
--- a/src/arch/arm/isa/templates/mem.isa Sat Jul 02 22:34:58 2011 -0700
+++ b/src/arch/arm/isa/templates/mem.isa Sat Jul 02 22:35:04 2011 -0700
@@ -209,7 +209,7 @@
if (%(predicate_test)s)
{
if (fault == NoFault) {
- fault = xc->readBytes(EA, dataPtr, %(size)d, memAccessFlags);
+ fault = xc->readMem(EA, dataPtr, %(size)d, memAccessFlags);
%(memacc_code)s;
}
@@ -280,8 +280,8 @@
}
if (fault == NoFault) {
- fault = xc->writeBytes(dataPtr, %(size)d, EA,
- memAccessFlags, NULL);
+ fault = xc->writeMem(dataPtr, %(size)d, EA,
+ memAccessFlags, NULL);
}
if (fault == NoFault) {
@@ -413,8 +413,8 @@
}
if (fault == NoFault) {
- fault = xc->writeBytes(memUnion.bytes, %(size)d, EA,
- memAccessFlags, NULL);
+ fault = xc->writeMem(memUnion.bytes, %(size)d, EA,
+ memAccessFlags, NULL);
}
} else {
xc->setPredicate(false);
@@ -467,7 +467,7 @@
if (%(predicate_test)s)
{
if (fault == NoFault) {
- fault = xc->readBytes(EA, dataPtr, %(size)d, memAccessFlags);
+ fault = xc->readMem(EA, dataPtr, %(size)d, memAccessFlags);
}
} else {
xc->setPredicate(false);
diff -r 530ff1bc8d70 -r 56de1f9320df src/arch/generic/memhelpers.hh
--- a/src/arch/generic/memhelpers.hh Sat Jul 02 22:34:58 2011 -0700
+++ b/src/arch/generic/memhelpers.hh Sat Jul 02 22:35:04 2011 -0700
@@ -42,7 +42,7 @@
readMemTiming(XC *xc, Trace::InstRecord *traceData, Addr addr,
MemT &mem, unsigned flags)
{
- return xc->readBytes(addr, (uint8_t *)&mem, sizeof(MemT), flags);
+ return xc->readMem(addr, (uint8_t *)&mem, sizeof(MemT), flags);
}
/// Extract the data returned from a timing mode read.
@@ -81,7 +81,7 @@
traceData->setData(mem);
}
mem = TheISA::htog(mem);
- return xc->writeBytes((uint8_t *)&mem, sizeof(MemT), addr, flags, res);
+ return xc->writeMem((uint8_t *)&mem, sizeof(MemT), addr, flags, res);
}
/// Write to memory in atomic mode.
diff -r 530ff1bc8d70 -r 56de1f9320df src/arch/x86/memhelpers.hh
--- a/src/arch/x86/memhelpers.hh Sat Jul 02 22:34:58 2011 -0700
+++ b/src/arch/x86/memhelpers.hh Sat Jul 02 22:35:04 2011 -0700
@@ -44,7 +44,7 @@
readMemTiming(XC *xc, Trace::InstRecord *traceData, Addr addr,
uint64_t &mem, unsigned dataSize, unsigned flags)
{
- return xc->readBytes(addr, (uint8_t *)&mem, dataSize, flags);
+ return xc->readMem(addr, (uint8_t *)&mem, dataSize, flags);
}
static inline uint64_t
@@ -99,7 +99,7 @@
traceData->setData(mem);
}
mem = TheISA::htog(mem);
- return xc->writeBytes((uint8_t *)&mem, dataSize, addr, flags, res);
+ return xc->writeMem((uint8_t *)&mem, dataSize, addr, flags, res);
}
template <class XC>
diff -r 530ff1bc8d70 -r 56de1f9320df src/cpu/base_dyn_inst.hh
--- a/src/cpu/base_dyn_inst.hh Sat Jul 02 22:34:58 2011 -0700
+++ b/src/cpu/base_dyn_inst.hh Sat Jul 02 22:35:04 2011 -0700
@@ -124,10 +124,10 @@
cpu->demapPage(vaddr, asn);
}
- Fault readBytes(Addr addr, uint8_t *data, unsigned size, unsigned flags);
+ Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags);
- Fault writeBytes(uint8_t *data, unsigned size,
- Addr addr, unsigned flags, uint64_t *res);
+ Fault writeMem(uint8_t *data, unsigned size,
+ Addr addr, unsigned flags, uint64_t *res);
/** Splits a request in two if it crosses a dcache block. */
void splitRequest(RequestPtr req, RequestPtr &sreqLow,
@@ -841,8 +841,8 @@
template<class Impl>
Fault
-BaseDynInst<Impl>::readBytes(Addr addr, uint8_t *data,
- unsigned size, unsigned flags)
+BaseDynInst<Impl>::readMem(Addr addr, uint8_t *data,
+ unsigned size, unsigned flags)
{
reqMade = true;
Request *req = NULL;
@@ -893,8 +893,8 @@
template<class Impl>
Fault
-BaseDynInst<Impl>::writeBytes(uint8_t *data, unsigned size,
- Addr addr, unsigned flags, uint64_t *res)
+BaseDynInst<Impl>::writeMem(uint8_t *data, unsigned size,
+ Addr addr, unsigned flags, uint64_t *res)
{
if (traceData) {
traceData->setAddr(addr);
diff -r 530ff1bc8d70 -r 56de1f9320df src/cpu/exec_context.hh
--- a/src/cpu/exec_context.hh Sat Jul 02 22:34:58 2011 -0700
+++ b/src/cpu/exec_context.hh Sat Jul 02 22:35:04 2011 -0700
@@ -106,10 +106,10 @@
/** Returns a pointer to the ThreadContext. */
ThreadContext *tcBase();
- Fault readBytes(Addr addr, uint8_t *data, unsigned size, unsigned flags);
+ Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags);
- Fault writeBytes(uint8_t *data, unsigned size,
- Addr addr, unsigned flags, uint64_t *res);
+ Fault writeMem(uint8_t *data, unsigned size,
+ Addr addr, unsigned flags, uint64_t *res);
#if FULL_SYSTEM
/** Somewhat Alpha-specific function that handles returning from
diff -r 530ff1bc8d70 -r 56de1f9320df src/cpu/inorder/inorder_dyn_inst.cc
--- a/src/cpu/inorder/inorder_dyn_inst.cc Sat Jul 02 22:34:58 2011 -0700
+++ b/src/cpu/inorder/inorder_dyn_inst.cc Sat Jul 02 22:35:04 2011 -0700
@@ -559,15 +559,15 @@
}
Fault
-InOrderDynInst::readBytes(Addr addr, uint8_t *data,
- unsigned size, unsigned flags)
+InOrderDynInst::readMem(Addr addr, uint8_t *data,
+ unsigned size, unsigned flags)
{
return cpu->read(this, addr, data, size, flags);
}
Fault
-InOrderDynInst::writeBytes(uint8_t *data, unsigned size,
- Addr addr, unsigned flags, uint64_t *res)
+InOrderDynInst::writeMem(uint8_t *data, unsigned size,
+ Addr addr, unsigned flags, uint64_t *res)
{
return cpu->write(this, data, size, addr, flags, res);
}
diff -r 530ff1bc8d70 -r 56de1f9320df src/cpu/inorder/inorder_dyn_inst.hh
--- a/src/cpu/inorder/inorder_dyn_inst.hh Sat Jul 02 22:34:58 2011 -0700
+++ b/src/cpu/inorder/inorder_dyn_inst.hh Sat Jul 02 22:35:04 2011 -0700
@@ -613,10 +613,10 @@
//
////////////////////////////////////////////
- Fault readBytes(Addr addr, uint8_t *data, unsigned size, unsigned flags);
+ Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags);
- Fault writeBytes(uint8_t *data, unsigned size,
- Addr addr, unsigned flags, uint64_t *res);
+ Fault writeMem(uint8_t *data, unsigned size,
+ Addr addr, unsigned flags, uint64_t *res);
/** Initiates a memory access - Calculate Eff. Addr & Initiate Memory
* Access Only valid for memory operations.
diff -r 530ff1bc8d70 -r 56de1f9320df src/cpu/simple/atomic.cc
--- a/src/cpu/simple/atomic.cc Sat Jul 02 22:34:58 2011 -0700
+++ b/src/cpu/simple/atomic.cc Sat Jul 02 22:35:04 2011 -0700
@@ -299,8 +299,8 @@
Fault
-AtomicSimpleCPU::readBytes(Addr addr, uint8_t * data,
- unsigned size, unsigned flags)
+AtomicSimpleCPU::readMem(Addr addr, uint8_t * data,
+ unsigned size, unsigned flags)
{
// use the CPU's statically allocated read request and packet objects
Request *req = &data_read_req;
@@ -387,8 +387,8 @@
Fault
-AtomicSimpleCPU::writeBytes(uint8_t *data, unsigned size,
- Addr addr, unsigned flags, uint64_t *res)
+AtomicSimpleCPU::writeMem(uint8_t *data, unsigned size,
+ Addr addr, unsigned flags, uint64_t *res)
{
// use the CPU's statically allocated write request and packet objects
Request *req = &data_write_req;
diff -r 530ff1bc8d70 -r 56de1f9320df src/cpu/simple/atomic.hh
--- a/src/cpu/simple/atomic.hh Sat Jul 02 22:34:58 2011 -0700
+++ b/src/cpu/simple/atomic.hh Sat Jul 02 22:35:04 2011 -0700
@@ -131,10 +131,10 @@
virtual void activateContext(int thread_num, int delay);
virtual void suspendContext(int thread_num);
- Fault readBytes(Addr addr, uint8_t *data, unsigned size, unsigned flags);
+ Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags);
- Fault writeBytes(uint8_t *data, unsigned size,
- Addr addr, unsigned flags, uint64_t *res);
+ Fault writeMem(uint8_t *data, unsigned size,
+ Addr addr, unsigned flags, uint64_t *res);
/**
* Print state of address in memory system via PrintReq (for
diff -r 530ff1bc8d70 -r 56de1f9320df src/cpu/simple/timing.cc
--- a/src/cpu/simple/timing.cc Sat Jul 02 22:34:58 2011 -0700
+++ b/src/cpu/simple/timing.cc Sat Jul 02 22:35:04 2011 -0700
@@ -432,8 +432,8 @@
}
Fault
-TimingSimpleCPU::readBytes(Addr addr, uint8_t *data,
- unsigned size, unsigned flags)
+TimingSimpleCPU::readMem(Addr addr, uint8_t *data,
+ unsigned size, unsigned flags)
{
Fault fault;
const int asid = 0;
@@ -500,8 +500,8 @@
}
Fault
-TimingSimpleCPU::writeBytes(uint8_t *data, unsigned size,
- Addr addr, unsigned flags, uint64_t *res)
+TimingSimpleCPU::writeMem(uint8_t *data, unsigned size,
+ Addr addr, unsigned flags, uint64_t *res)
{
uint8_t *newData = new uint8_t[size];
memcpy(newData, data, size);
diff -r 530ff1bc8d70 -r 56de1f9320df src/cpu/simple/timing.hh
--- a/src/cpu/simple/timing.hh Sat Jul 02 22:34:58 2011 -0700
+++ b/src/cpu/simple/timing.hh Sat Jul 02 22:35:04 2011 -0700
@@ -256,10 +256,10 @@
virtual void activateContext(int thread_num, int delay);
virtual void suspendContext(int thread_num);
- Fault readBytes(Addr addr, uint8_t *data, unsigned size, unsigned flags);
+ Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags);
- Fault writeBytes(uint8_t *data, unsigned size,
- Addr addr, unsigned flags, uint64_t *res);
+ Fault writeMem(uint8_t *data, unsigned size,
+ Addr addr, unsigned flags, uint64_t *res);
void fetch();
void sendFetch(Fault fault, RequestPtr req, ThreadContext *tc);
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