changeset 4be49ad47c74 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=4be49ad47c74
description:
ISA parser: Define operand types with a ctype directly.
diffstat:
src/arch/alpha/isa/main.isa | 20 ++++++++++----------
src/arch/arm/isa/operands.isa | 20 ++++++++++----------
src/arch/isa_parser.py | 28 +---------------------------
src/arch/mips/isa/operands.isa | 20 ++++++++++----------
src/arch/power/isa/operands.isa | 20 ++++++++++----------
src/arch/sparc/isa/operands.isa | 25 ++++++++++++-------------
src/arch/x86/isa/operands.isa | 20 ++++++++++----------
7 files changed, 63 insertions(+), 90 deletions(-)
diffs (235 lines):
diff -r 86ed97566b23 -r 4be49ad47c74 src/arch/alpha/isa/main.isa
--- a/src/arch/alpha/isa/main.isa Tue Jul 05 16:48:18 2011 -0700
+++ b/src/arch/alpha/isa/main.isa Tue Jul 05 16:52:15 2011 -0700
@@ -161,16 +161,16 @@
def bitfield M5FUNC <7:0>;
def operand_types {{
- 'sb' : ('signed int', 8),
- 'ub' : ('unsigned int', 8),
- 'sw' : ('signed int', 16),
- 'uw' : ('unsigned int', 16),
- 'sl' : ('signed int', 32),
- 'ul' : ('unsigned int', 32),
- 'sq' : ('signed int', 64),
- 'uq' : ('unsigned int', 64),
- 'sf' : ('float', 32),
- 'df' : ('float', 64)
+ 'sb' : 'int8_t',
+ 'ub' : 'uint8_t',
+ 'sw' : 'int16_t',
+ 'uw' : 'uint16_t',
+ 'sl' : 'int32_t',
+ 'ul' : 'uint32_t',
+ 'sq' : 'int64_t',
+ 'uq' : 'uint64_t',
+ 'sf' : 'float',
+ 'df' : 'double'
}};
def operands {{
diff -r 86ed97566b23 -r 4be49ad47c74 src/arch/arm/isa/operands.isa
--- a/src/arch/arm/isa/operands.isa Tue Jul 05 16:48:18 2011 -0700
+++ b/src/arch/arm/isa/operands.isa Tue Jul 05 16:52:15 2011 -0700
@@ -40,16 +40,16 @@
// Authors: Stephen Hines
def operand_types {{
- 'sb' : ('signed int', 8),
- 'ub' : ('unsigned int', 8),
- 'sh' : ('signed int', 16),
- 'uh' : ('unsigned int', 16),
- 'sw' : ('signed int', 32),
- 'uw' : ('unsigned int', 32),
- 'ud' : ('unsigned int', 64),
- 'tud' : ('twin64 int', 64),
- 'sf' : ('float', 32),
- 'df' : ('float', 64)
+ 'sb' : 'int8_t',
+ 'ub' : 'uint8_t',
+ 'sh' : 'int16_t',
+ 'uh' : 'uint16_t',
+ 'sw' : 'int32_t',
+ 'uw' : 'uint32_t',
+ 'ud' : 'uint64_t',
+ 'tud' : 'Twin64_t',
+ 'sf' : 'float',
+ 'df' : 'double'
}};
let {{
diff -r 86ed97566b23 -r 4be49ad47c74 src/arch/isa_parser.py
--- a/src/arch/isa_parser.py Tue Jul 05 16:48:18 2011 -0700
+++ b/src/arch/isa_parser.py Tue Jul 05 16:52:15 2011 -0700
@@ -1321,13 +1321,12 @@
def p_def_operand_types(self, t):
'def_operand_types : DEF OPERAND_TYPES CODELIT SEMI'
try:
- user_dict = eval('{' + t[3] + '}')
+ self.operandTypeMap = eval('{' + t[3] + '}')
except Exception, exc:
if debug:
raise
error(t,
'error: %s in def operand_types block "%s".' % (exc, t[3]))
- self.buildOperandTypeMap(user_dict, t.lexer.lineno)
t[0] = GenCode(self) # contributes nothing to the output C++ file
# Define the mapping from operand names to operand classes and
@@ -1788,31 +1787,6 @@
return re.sub(r'%(?!\()', '%%', s)
- def buildOperandTypeMap(self, user_dict, lineno):
- """Generate operandTypeMap from the user's 'def operand_types'
- statement."""
- operand_type = {}
- for (ext, (desc, size)) in user_dict.iteritems():
- if desc == 'signed int':
- ctype = 'int%d_t' % size
- elif desc == 'unsigned int':
- ctype = 'uint%d_t' % size
- elif desc == 'float':
- if size == 32:
- ctype = 'float'
- elif size == 64:
- ctype = 'double'
- elif desc == 'twin64 int':
- ctype = 'Twin64_t'
- elif desc == 'twin32 int':
- ctype = 'Twin32_t'
- if ctype == '':
- error(parser, lineno,
- 'Unrecognized type description "%s" in user_dict')
- operand_type[ext] = ctype
-
- self.operandTypeMap = operand_type
-
def buildOperandNameMap(self, user_dict, lineno):
operand_name = {}
for op_name, val in user_dict.iteritems():
diff -r 86ed97566b23 -r 4be49ad47c74 src/arch/mips/isa/operands.isa
--- a/src/arch/mips/isa/operands.isa Tue Jul 05 16:48:18 2011 -0700
+++ b/src/arch/mips/isa/operands.isa Tue Jul 05 16:52:15 2011 -0700
@@ -30,16 +30,16 @@
// Jaidev Patwardhan
def operand_types {{
- 'sb' : ('signed int', 8),
- 'ub' : ('unsigned int', 8),
- 'sh' : ('signed int', 16),
- 'uh' : ('unsigned int', 16),
- 'sw' : ('signed int', 32),
- 'uw' : ('unsigned int', 32),
- 'sd' : ('signed int', 64),
- 'ud' : ('unsigned int', 64),
- 'sf' : ('float', 32),
- 'df' : ('float', 64),
+ 'sb' : 'int8_t',
+ 'ub' : 'uint8_t',
+ 'sh' : 'int16_t',
+ 'uh' : 'uint16_t',
+ 'sw' : 'int32_t',
+ 'uw' : 'uint32_t',
+ 'sd' : 'int64_t',
+ 'ud' : 'uint64_t',
+ 'sf' : 'float',
+ 'df' : 'double'
}};
def operands {{
diff -r 86ed97566b23 -r 4be49ad47c74 src/arch/power/isa/operands.isa
--- a/src/arch/power/isa/operands.isa Tue Jul 05 16:48:18 2011 -0700
+++ b/src/arch/power/isa/operands.isa Tue Jul 05 16:52:15 2011 -0700
@@ -29,16 +29,16 @@
// Authors: Timothy M. Jones
def operand_types {{
- 'sb' : ('signed int', 8),
- 'ub' : ('unsigned int', 8),
- 'sh' : ('signed int', 16),
- 'uh' : ('unsigned int', 16),
- 'sw' : ('signed int', 32),
- 'uw' : ('unsigned int', 32),
- 'sq' : ('signed int', 64),
- 'uq' : ('unsigned int', 64),
- 'sf' : ('float', 32),
- 'df' : ('float', 64)
+ 'sb' : 'int8_t',
+ 'ub' : 'uint8_t',
+ 'sh' : 'int16_t',
+ 'uh' : 'uint16_t',
+ 'sw' : 'int32_t',
+ 'uw' : 'uint32_t',
+ 'sq' : 'int64_t',
+ 'uq' : 'uint64_t',
+ 'sf' : 'float',
+ 'df' : 'double'
}};
def operands {{
diff -r 86ed97566b23 -r 4be49ad47c74 src/arch/sparc/isa/operands.isa
--- a/src/arch/sparc/isa/operands.isa Tue Jul 05 16:48:18 2011 -0700
+++ b/src/arch/sparc/isa/operands.isa Tue Jul 05 16:52:15 2011 -0700
@@ -29,19 +29,18 @@
// Steve Reinhardt
def operand_types {{
- 'sb' : ('signed int', 8),
- 'ub' : ('unsigned int', 8),
- 'shw' : ('signed int', 16),
- 'uhw' : ('unsigned int', 16),
- 'sw' : ('signed int', 32),
- 'uw' : ('unsigned int', 32),
- 'sdw' : ('signed int', 64),
- 'udw' : ('unsigned int', 64),
- 'tudw' : ('twin64 int', 64),
- 'tuw' : ('twin32 int', 32),
- 'sf' : ('float', 32),
- 'df' : ('float', 64),
- 'qf' : ('float', 128)
+ 'sb' : 'int8_t',
+ 'ub' : 'uint8_t',
+ 'shw' : 'int16_t',
+ 'uhw' : 'uint16_t',
+ 'sw' : 'int32_t',
+ 'uw' : 'uint32_t',
+ 'sdw' : 'int64_t',
+ 'udw' : 'uint64_t',
+ 'tudw' : 'Twin64_t',
+ 'tuw' : 'Twin32_t',
+ 'sf' : 'float',
+ 'df' : 'double'
}};
output header {{
diff -r 86ed97566b23 -r 4be49ad47c74 src/arch/x86/isa/operands.isa
--- a/src/arch/x86/isa/operands.isa Tue Jul 05 16:48:18 2011 -0700
+++ b/src/arch/x86/isa/operands.isa Tue Jul 05 16:52:15 2011 -0700
@@ -39,16 +39,16 @@
// Authors: Gabe Black
def operand_types {{
- 'sb' : ('signed int', 8),
- 'ub' : ('unsigned int', 8),
- 'sw' : ('signed int', 16),
- 'uw' : ('unsigned int', 16),
- 'sdw' : ('signed int', 32),
- 'udw' : ('unsigned int', 32),
- 'sqw' : ('signed int', 64),
- 'uqw' : ('unsigned int', 64),
- 'sf' : ('float', 32),
- 'df' : ('float', 64),
+ 'sb' : 'int8_t',
+ 'ub' : 'uint8_t',
+ 'sw' : 'int16_t',
+ 'uw' : 'uint16_t',
+ 'sdw' : 'int32_t',
+ 'udw' : 'uint32_t',
+ 'sqw' : 'int64_t',
+ 'uqw' : 'uint64_t',
+ 'sf' : 'float',
+ 'df' : 'double',
}};
let {{
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