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src/cpu/o3/inst_queue_impl.hh <http://reviews.m5sim.org/r/767/#comment1838> Could you explain what is going on here? Previously these instructions did what? Sat here until the squash propagated? Is there a corner case of the translation currently being in progress and the instruction getting squashed and removed before this comes back? - Ali On 2011-07-03 03:37:29, Gabe Black wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.m5sim.org/r/767/ > ----------------------------------------------------------- > > (Updated 2011-07-03 03:37:29) > > > Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and > Nathan Binkert. > > > Summary > ------- > > O3: Let squashed and deferred instructions issue. > > Let squahsed and deferred instructions issue so they don't accumulate and clog > up the CPU. > > > Diffs > ----- > > src/cpu/o3/inst_queue_impl.hh 1b4b9c05ad2b > > Diff: http://reviews.m5sim.org/r/767/diff > > > Testing > ------- > > > Thanks, > > Gabe > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
