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I ran the X86 regressions with these patches and my uncommitted X86_FS patches, and other than some expected stat differences everything seems ok. It looks like the bulk of this patch is actually changes to the DPRINTFs. That should go in a separate patch since it isn't integral to what this one is trying to do. It should be trivial to separate out and they can be submitted next to each other. Minor style nits are noted. src/cpu/o3/mem_dep_unit_impl.hh <http://reviews.m5sim.org/r/793/#comment1856> space after the comma src/cpu/o3/mem_dep_unit_impl.hh <http://reviews.m5sim.org/r/793/#comment1857> space between if and ( here and below - Gabe On 2011-07-15 09:41:50, Ali Saidi wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.m5sim.org/r/793/ > ----------------------------------------------------------- > > (Updated 2011-07-15 09:41:50) > > > Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and > Nathan Binkert. > > > Summary > ------- > > LSQ: Fix a few issues with the storeset predictor. > > Two issues are fixed in this patch: > 1. The load and store pc passed to the predictor are passed in reverse order. > 2. The flag indicating that a barrier is inflight was never cleared when > the barrier was squashed instead of committed. This made all load insts > dependent on a non-existent barrier in-flight. > > > Diffs > ----- > > src/cpu/o3/commit_impl.hh 82ff928182c5 > src/cpu/o3/mem_dep_unit.hh 82ff928182c5 > src/cpu/o3/mem_dep_unit_impl.hh 82ff928182c5 > > Diff: http://reviews.m5sim.org/r/793/diff > > > Testing > ------- > > > Thanks, > > Ali > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
