hi Steve and Brad,

I updated to the latest version of the repo and the problem persists.

Specifically, I did the same experiment Steve suggested (added the
same 2 lines in src/sim/System.py and src/sim/system.cc) and I got the
same segmentation fault I get when I add an integer vector into my
fault model python file:

----------------------------
kaisopos@hermes1:~/GEM5_Fault_Model/gem5$ build/ALPHA_SE/gem5.debug
configs/example/se.py
gem5 Simulator System.  http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.

gem5 compiled Jul 27 2011 19:23:03
gem5 started Jul 27 2011 19:24:15
gem5 executing on hermes1
command line: build/ALPHA_SE/gem5.debug configs/example/se.py
Global frequency set at 1000000000000 ticks per second
Traceback (most recent call last):
  File "<string>", line 1, in <module>
  File "/data/lsp/kaisopos/GEM5_Fault_Model/gem5/src/python/m5/main.py",
line 356, in main
    exec filecode in scope
  File "configs/example/se.py", line 199, in <module>
    Simulation.run(options, root, system, FutureClass)
  File "/data/lsp/kaisopos/GEM5_Fault_Model/gem5/configs/common/Simulation.py",
line 235, in run
    m5.instantiate(checkpoint_dir)
  File "/data/lsp/kaisopos/GEM5_Fault_Model/gem5/src/python/m5/simulate.py",
line 78, in instantiate
    for obj in root.descendants(): obj.createCCObject()
  File "/data/lsp/kaisopos/GEM5_Fault_Model/gem5/src/python/m5/SimObject.py",
line 881, in createCCObject
    self.getCCParams()
  File "/data/lsp/kaisopos/GEM5_Fault_Model/gem5/src/python/m5/SimObject.py",
line 840, in getCCParams
    assert not len(vec)
TypeError: object of type 'PySwigObject' has no len()
----------------------------

I am using the latest code (I did "hg pull -u" right before compiling)
I am using Python 2.5.2 and SWIG 1.3.36
If the same code worked for both of you, the problem has to be either
Python or SWIG, right?
or is there any other possible explanation? any other thoughts?

thanks all of you for helping out,
-Kostas

On Wed, Jul 27, 2011 at 4:38 PM, Steve Reinhardt <[email protected]> wrote:
> Weird... I don't see any changes in the last three weeks that would have
> affected that.
> Thanks for figuring that out though, Brad.
> Steve
>
> On Wed, Jul 27, 2011 at 1:27 PM, Beckmann, Brad <[email protected]>
> wrote:
>>
>> Hi Konstantinos,
>>
>> FYI, I was able to reproduce your error when I used a 3-week old version
>> of the repo.  However, I updated to the latest version of the repo and the
>> problem appears fixed.  I can now reproduce the correct behavior that Steve
>> observed.
>>
>> Brad
>>
>>
>> > -----Original Message-----
>> > From: [email protected] [mailto:gem5-dev-
>> > [email protected]] On Behalf Of Steve Reinhardt
>> > Sent: Wednesday, July 27, 2011 8:25 AM
>> > To: Konstantinos Aisopos; Default
>> > Subject: Re: [gem5-dev] Review Request: GARNET: adding a fault model for
>> > resilient on-chip network research.
>> >
>> > (Getting this off of reviewboard so it's easier to reply...)
>> >
>> > Hi Konstantinos,
>> >
>> > I just made this change at the head of the tree:
>> >
>> > diff --git a/src/sim/System.py b/src/sim/System.py
>> > --- a/src/sim/System.py
>> > +++ b/src/sim/System.py
>> > @@ -44,6 +44,8 @@
>> >      def swig_objdecls(cls, code):
>> >          code('%include "python/swig/system.i"')
>> >
>> > +    test = VectorParam.Int([1, 2, 3], "")
>> > +
>> >      physmem = Param.PhysicalMemory("Physical Memory")
>> >      mem_mode = Param.MemoryMode('atomic', "The mode the memory
>> > system is
>> > in")
>> >      memories = VectorParam.PhysicalMemory(Self.all, "All memories is
>> > the
>> > system")
>> > diff --git a/src/sim/system.cc b/src/sim/system.cc
>> > --- a/src/sim/system.cc
>> > +++ b/src/sim/system.cc
>> > @@ -83,6 +83,8 @@
>> >      // add self to global system list
>> >      systemList.push_back(this);
>> >
>> > +    cprintf("%s.test: len %d, %d\n", name(), p->test.size(),
>> > + p->test[0]);
>> > +
>> >      /** Keep track of all memories we can execute code out of
>> >       * in our system
>> >       */
>> >
>> >
>> > and it worked:
>> >
>> > % build/ALPHA_SE/gem5.debug configs/example/se.py
>> > gem5 Simulator System.  http://gem5.org
>> > gem5 is copyrighted software; use the --copyright option for details.
>> >
>> > gem5 compiled Jul 27 2011 08:19:34
>> > gem5 started Jul 27 2011 08:19:42
>> > gem5 executing on phenom
>> > command line: build/ALPHA_SE/gem5.debug configs/example/se.py Global
>> > frequency set at 1000000000000 ticks per second
>> > system.test: len 3, 1
>> > 0: system.remote_gdb.listener: listening for remote gdb #0 on port 7000
>> > **** REAL SIMULATION ****
>> > info: Entering event queue @ 0.  Starting simulation...
>> > info: Increasing stack size by one page.
>> > Hello world!
>> > hack: be nice to actually delete the event here Exiting @ tick 3256000
>> > because target called exit()
>> >
>> > So it's not clear to me why it's not working for you... are you at the
>> > tip of the
>> > gem5 repository?  What versions of Python and SWIG are you using?  I
>> > have
>> > 2.6.5 and 1.3.40, respectively.
>> >
>> > Steve
>> > _______________________________________________
>> > gem5-dev mailing list
>> > [email protected]
>> > http://m5sim.org/mailman/listinfo/gem5-dev
>>
>>
>> _______________________________________________
>> gem5-dev mailing list
>> [email protected]
>> http://m5sim.org/mailman/listinfo/gem5-dev
>
>
_______________________________________________
gem5-dev mailing list
[email protected]
http://m5sim.org/mailman/listinfo/gem5-dev

Reply via email to