----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/843/ -----------------------------------------------------------
(Updated 2011-09-08 04:00:02.263856) Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan Binkert. Summary (updated) ------- imported patch 4.6.1fixes.patch Diffs (updated) ----- src/SConscript b324639974f6 src/arch/alpha/ev5.cc b324639974f6 src/arch/alpha/isa/decoder.isa b324639974f6 src/arch/alpha/isa/mem.isa b324639974f6 src/arch/arm/isa/formats/fp.isa b324639974f6 src/arch/arm/isa/insts/fp.isa b324639974f6 src/arch/arm/isa/insts/m5ops.isa b324639974f6 src/arch/arm/isa/insts/macromem.isa b324639974f6 src/arch/arm/isa/insts/neon.isa b324639974f6 src/arch/arm/isa/templates/mem.isa b324639974f6 src/arch/mips/isa/decoder.isa b324639974f6 src/arch/mips/isa/formats/control.isa b324639974f6 src/arch/mips/isa/formats/mt.isa b324639974f6 src/arch/mips/isa/includes.isa b324639974f6 src/arch/mips/tlb.cc b324639974f6 src/arch/power/isa/formats/mem.isa b324639974f6 src/arch/power/tlb.cc b324639974f6 src/arch/sparc/isa/formats/mem/util.isa b324639974f6 src/arch/x86/isa/microops/base.isa b324639974f6 src/base/inet.cc b324639974f6 src/cpu/base.cc b324639974f6 src/cpu/inorder/cpu.cc b324639974f6 src/cpu/legiontrace.cc b324639974f6 src/cpu/o3/cpu.cc b324639974f6 src/cpu/o3/rename_impl.hh b324639974f6 src/mem/cache/tags/iic.cc b324639974f6 src/mem/ruby/network/orion/Clock.cc b324639974f6 src/mem/ruby/system/PersistentTable.hh b324639974f6 src/mem/ruby/system/PseudoLRUPolicy.hh b324639974f6 src/python/m5/params.py b324639974f6 src/python/swig/pyobject.cc b324639974f6 src/sim/pseudo_inst.hh b324639974f6 Diff: http://reviews.m5sim.org/r/843/diff Testing ------- Thanks, Gabe _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
