> On Feb. 9, 2012, 1:55 a.m., Gabe Black wrote: > > src/cpu/checker/cpu_impl.hh, line 402 > > <http://reviews.gem5.org/r/1031/diff/1/?file=23033#file23033line402> > > > > Why does this need to be FullSystem only? > > Geoffrey Blake wrote: > Yes. In SE mode faults just happen and no PC change occurs right? Only > in FS will the PC be vectored to a fault handler. > > Gabe Black wrote: > No. In SE faults *usually* just happen (typically panicing or updating > the TLB), but that's not a hard rule. In SPARC specifically there are faults > that do register window spills and fills in SE mode in actual handlers > injected into memory before the process starts. > > Geoffrey Blake wrote: > That's a good bit of info to know if someone wants to use the Checker > with the SPARC ISA. But since I'm only worried about it working with ARM for > now I'll put this off to the side right now. > > Gabe Black wrote: > I don't think it's a good idea to build in an assumption like that, > especially since it shouldn't be that hard to fix (you can actually check if > the PC changed once you invoke the fault). As a matter of fact, to further > unify SE and FS, I'm planning to make all faults/syscalls in all ISAs > actually use the normal mechanisms to vector tables/whatever injected into > memory which hold pseudo ops that cause the emulated behavior, panics, etc.
Part of the problem right now is that in SE mode the fault will be re-executed, and not all syscalls and fault handlers do idempotent operations. This will have to be fixed with some sort of logic that won't let the fault do something to the state if its called from the Checker. I'm not sure what should be done for this. This problem is avoided in FS operation because the Checker never updates memory. - Geoffrey ----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/1031/#review2098 ----------------------------------------------------------- On Feb. 17, 2012, 10:09 a.m., Geoffrey Blake wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/1031/ > ----------------------------------------------------------- > > (Updated Feb. 17, 2012, 10:09 a.m.) > > > Review request for Default. > > > Description > ------- > > CheckerCPU: Make CheckerCPU runtime selectable instead of compile selectable > > Enables the CheckerCPU to be enabled at runtime with the --checker option > from the configs/example/fs.py and configs/example/se.py configuration > files. Also merges with the SE/FS changes. > > > Diffs > ----- > > SConstruct ef8630054b5e > configs/common/Options.py ef8630054b5e > configs/common/Simulation.py ef8630054b5e > configs/example/fs.py ef8630054b5e > configs/example/se.py ef8630054b5e > src/arch/SConscript ef8630054b5e > src/arch/arm/isa.cc ef8630054b5e > src/arch/arm/utility.cc ef8630054b5e > src/cpu/BaseCPU.py ef8630054b5e > src/cpu/SConscript ef8630054b5e > src/cpu/base.cc ef8630054b5e > src/cpu/base_dyn_inst.hh ef8630054b5e > src/cpu/base_dyn_inst_impl.hh ef8630054b5e > src/cpu/checker/cpu.hh ef8630054b5e > src/cpu/checker/cpu.cc ef8630054b5e > src/cpu/checker/cpu_impl.hh ef8630054b5e > src/cpu/checker/thread_context.hh ef8630054b5e > src/cpu/o3/O3CPU.py ef8630054b5e > src/cpu/o3/SConscript ef8630054b5e > src/cpu/o3/commit_impl.hh ef8630054b5e > src/cpu/o3/cpu.hh ef8630054b5e > src/cpu/o3/cpu.cc ef8630054b5e > src/cpu/o3/cpu_builder.cc ef8630054b5e > src/cpu/o3/dyn_inst_impl.hh ef8630054b5e > src/cpu/o3/fetch_impl.hh ef8630054b5e > src/cpu/o3/iew_impl.hh ef8630054b5e > src/cpu/o3/lsq_unit_impl.hh ef8630054b5e > src/cpu/o3/thread_context.hh ef8630054b5e > src/cpu/o3/thread_context_impl.hh ef8630054b5e > src/cpu/ozone/OzoneCPU.py ef8630054b5e > src/cpu/ozone/SConscript ef8630054b5e > src/cpu/ozone/cpu_impl.hh ef8630054b5e > src/cpu/ozone/front_end_impl.hh ef8630054b5e > src/cpu/ozone/lw_back_end_impl.hh ef8630054b5e > src/cpu/ozone/lw_lsq_impl.hh ef8630054b5e > src/cpu/simple/BaseSimpleCPU.py ef8630054b5e > src/cpu/simple/base.hh ef8630054b5e > src/cpu/simple/base.cc ef8630054b5e > src/cpu/simple_thread.hh ef8630054b5e > src/cpu/thread_context.hh ef8630054b5e > > Diff: http://reviews.gem5.org/r/1031/diff/diff > > > Testing > ------- > > Compiles with ARM ISA. > Boots linux with O3 model attached to Checker in FS mode. > Runs simple HelloWorld in SE mode. > > > Thanks, > > Geoffrey Blake > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
