changeset 97f06a79b6f5 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=97f06a79b6f5
description:
X86: Fix address size handling so real mode works properly.
Virtual (pre-segmentation) addresses are truncated based on address
size, and
any non-64 bit linear address is truncated to 32 bits. This means that
real
mode addresses aren't truncated down to 16 bits after their segment
bases are
added in.
diffstat:
src/arch/x86/isa/microops/ldstop.isa | 2 +-
src/arch/x86/tlb.cc | 3 +++
2 files changed, 4 insertions(+), 1 deletions(-)
diffs (25 lines):
diff -r 5f6cfd09fdaf -r 97f06a79b6f5 src/arch/x86/isa/microops/ldstop.isa
--- a/src/arch/x86/isa/microops/ldstop.isa Fri Mar 30 12:57:48 2012 -0400
+++ b/src/arch/x86/isa/microops/ldstop.isa Sat Mar 31 12:27:33 2012 -0700
@@ -361,7 +361,7 @@
exec_output = ""
calculateEA = '''
- EA = bits(SegBase + scale * Index + Base + disp, addressSize * 8 - 1, 0);
+ EA = SegBase + bits(scale * Index + Base + disp, addressSize * 8 - 1, 0);
'''
def defineMicroLoadOp(mnemonic, code, bigCode='',
diff -r 5f6cfd09fdaf -r 97f06a79b6f5 src/arch/x86/tlb.cc
--- a/src/arch/x86/tlb.cc Fri Mar 30 12:57:48 2012 -0400
+++ b/src/arch/x86/tlb.cc Sat Mar 31 12:27:33 2012 -0700
@@ -281,6 +281,9 @@
return new GeneralProtection(0);
}
}
+ if (m5Reg.mode != LongMode ||
+ (flags & (AddrSizeFlagBit << FlagShift)))
+ vaddr &= mask(32);
// If paging is enabled, do the translation.
if (m5Reg.paging) {
DPRINTF(TLB, "Paging enabled.\n");
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