Check out this old proposal. I have some code to support it, but it's not complete.
Nate ---------- Forwarded message ---------- From: nathan binkert <[email protected]> Date: Mon, Apr 26, 2010 at 11:45 AM Subject: Re: [m5-dev] curTick + 1 bugs in Memory System? To: M5 Developer List <[email protected]> Basically, the idea was to create a ClockedObject that derived from SimObject and had the notion of a clock period and phase and a couple helper functions for scheduling events on clock edges. (The default period and phase would be Parent.clock and Parent.clock_phase) I more or less have all of the pieces together. We could easily just change a bunch of classes that derive from SimObject to instead derive from ClockedObject. Another nice feature is that I've added support for specifying latencies in terms of cycles for clocked objects. So just as you can say '3ns' or '1t', you can now say '3c' which means 3 cycle latency. 3c essentially gets translated to "3 * Self.clock.latency" I can try to get those changes to the head of my patch queue and send them out for review. Nate _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
