> On April 25, 2012, 7:37 a.m., Steve Reinhardt wrote:
> > I believe I understand why this is necessary,
> 
> Steve Reinhardt wrote:
>     Oops, clicked "publish" instead of "save" by accident...
>     
>     My concern is that we are adding an array to every instruction, and a 
> level of indirection to every register access, when the vast majority of the 
> time this is an identity mapping.  And "vast majority" will be 100% for many 
> ISAs.  I don't know how significant the performance impact will be, but I'm 
> confident that it will not be in the right direction.
>     
>     I don't have a specific proposal to avoid this, but I don't want to see 
> this code go in lightly without consideration of the performance impact.

I second this concern.


- Ali


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On April 24, 2012, 2:13 p.m., Nilay Vaish wrote:
> 
> -----------------------------------------------------------
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.gem5.org/r/1153/
> -----------------------------------------------------------
> 
> (Updated April 24, 2012, 2:13 p.m.)
> 
> 
> Review request for Default.
> 
> 
> Description
> -------
> 
> Changeset 8966:c8c03cb78aa1
> ---------------------------
> ISA Parser: Decide source register indices at runtime
> Currently the register indices for source and destination registers are 
> decided
> statically by the isa parser. This patch moves this decision to run time. This
> will be useful when register will be read based on a condition specified while
> construction of a microop.
> 
> 
> Diffs
> -----
> 
>   src/arch/isa_parser.py 91a6f8f07074 
>   src/cpu/static_inst.hh 91a6f8f07074 
> 
> Diff: http://reviews.gem5.org/r/1153/diff/
> 
> 
> Testing
> -------
> 
> 
> Thanks,
> 
> Nilay Vaish
> 
>

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