It seems over the last week we have converged on using the zero register
(which is only available to the microcode) for avoiding RAW dependences on
condition code register while using o3 cpu. There is one slight issue
here. Earlier I had posted a patch that lets the ISA specify predicates /
conditions for reading and writing operands. These predicates are
evaluated when the instruction object is being constructed. The issue is
we need separate conditions for reading and writing the condition code
register. ARM handles it by specifying different names for the source and
destination register. For example --
'CondCodesNZ': intRegCC('INTREG_CONDCODES_NZ'),
'OptCondCodesNZ': intRegCC(
'''(condCode == COND_AL || condCode == COND_UC ||
condCode == COND_CC || condCode == COND_CS ||
condCode == COND_VS || condCode == COND_VC) ?
INTREG_ZERO : INTREG_CONDCODES_NZ'''),
So should we go the same way for x86 as well?
--
Nilay
_______________________________________________
gem5-dev mailing list
[email protected]
http://m5sim.org/mailman/listinfo/gem5-dev
