On 04/30/12 09:01, Nilay Vaish wrote:
> It seems over the last week we have converged on using the zero
> register (which is only available to the microcode) for avoiding RAW
> dependences on condition code register while using o3 cpu. There is
> one slight issue here. Earlier I had posted a patch that lets the ISA
> specify predicates / conditions for reading and writing operands.
> These predicates are evaluated when the instruction object is being
> constructed. The issue is we need separate conditions for reading and
> writing the condition code register. ARM handles it by specifying
> different names for the source and destination register. For example --
>
> 'CondCodesNZ': intRegCC('INTREG_CONDCODES_NZ'),
>
> 'OptCondCodesNZ': intRegCC(
> '''(condCode == COND_AL || condCode == COND_UC ||
> condCode == COND_CC || condCode == COND_CS ||
> condCode == COND_VS || condCode == COND_VC) ?
> INTREG_ZERO : INTREG_CONDCODES_NZ'''),
>
>
> So should we go the same way for x86 as well?
>
> --
> Nilay
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Those are not separate names for the source and destination registers,
those are two names for the same thing. The difference between the two
is the behavior you're selecting as far as whether the operand will be
unconditionally used (the first one) or if it will decide to turn itself
on or off based on the instruction's predicate (the second one). The
second one is used if the condition codes are only going to be used by
the predicate logic, and the first is if they're going to be used for
something else too which isn't gated on whether or not the predicate
actually consumes condition code bits.
Gabe
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