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Hi Andreas, This looks reasonable to me. Before you commit it though, I'm curious about your longer-term vision for handling different protocols. It's hard for me to feel completely confident in the naming and in the functionality split without a better idea of where you're headed. For example, I'd think that sending and receiving are pretty basic operations as well, so should there be some form of send and receive in the base ports as well? I can also see where if the packet class varies from protocol to protocol you don't want to hardwire that (but you could have a base packet class as well, which could be hardwired as the class for send/receive on the base ports). Clearly there are a lot of ways to do it, and I don't know which one you have in mind. This is probably something that's worth it's own email thread rather than doing it all in reviewboard comments... src/mem/port.hh <http://reviews.gem5.org/r/1273/#comment3234> typo "overrive" - Steve Reinhardt On June 17, 2012, 10:18 a.m., Andreas Hansson wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/1273/ > ----------------------------------------------------------- > > (Updated June 17, 2012, 10:18 a.m.) > > > Review request for Default. > > > Description > ------- > > Changeset 9081:944fe8294fa3 > --------------------------- > Port: Add protocol-agnostic ports in the port hierarchy > > This patch adds an additional level of ports in the inheritance > hierarchy, separating out the protocol-specific and protocl-agnostic > parts. All the functionality related to the binding of ports is now > confined to use BaseMaster/BaseSlavePorts, and all the > protocol-specific parts stay in the Master/SlavePort. In the future it > will be possible to add other protocol-specific implementations. > > The functions used in the binding of ports, i.e. getMaster/SlavePort > now use the base classes, and the index parameter is updated to use > the PortID typedef with the symbolic InvalidPortID as the default. > > > Diffs > ----- > > src/arch/arm/table_walker.hh fa77985a87c6 > src/arch/arm/table_walker.cc fa77985a87c6 > src/arch/arm/tlb.hh fa77985a87c6 > src/arch/arm/tlb.cc fa77985a87c6 > src/arch/x86/interrupts.hh fa77985a87c6 > src/arch/x86/pagetable_walker.hh fa77985a87c6 > src/arch/x86/pagetable_walker.cc fa77985a87c6 > src/arch/x86/tlb.hh fa77985a87c6 > src/arch/x86/tlb.cc fa77985a87c6 > src/cpu/base.hh fa77985a87c6 > src/cpu/base.cc fa77985a87c6 > src/cpu/testers/directedtest/RubyDirectedTester.hh fa77985a87c6 > src/cpu/testers/directedtest/RubyDirectedTester.cc fa77985a87c6 > src/cpu/testers/memtest/memtest.hh fa77985a87c6 > src/cpu/testers/memtest/memtest.cc fa77985a87c6 > src/cpu/testers/networktest/networktest.hh fa77985a87c6 > src/cpu/testers/networktest/networktest.cc fa77985a87c6 > src/cpu/testers/rubytest/RubyTester.hh fa77985a87c6 > src/cpu/testers/rubytest/RubyTester.cc fa77985a87c6 > src/dev/copy_engine.hh fa77985a87c6 > src/dev/copy_engine.cc fa77985a87c6 > src/dev/dma_device.hh fa77985a87c6 > src/dev/dma_device.cc fa77985a87c6 > src/dev/io_device.hh fa77985a87c6 > src/dev/io_device.cc fa77985a87c6 > src/dev/pcidev.hh fa77985a87c6 > src/dev/x86/i82094aa.hh fa77985a87c6 > src/mem/bridge.hh fa77985a87c6 > src/mem/bridge.cc fa77985a87c6 > src/mem/bus.hh fa77985a87c6 > src/mem/bus.cc fa77985a87c6 > src/mem/cache/base.hh fa77985a87c6 > src/mem/cache/base.cc fa77985a87c6 > src/mem/comm_monitor.hh fa77985a87c6 > src/mem/comm_monitor.cc fa77985a87c6 > src/mem/mem_object.hh fa77985a87c6 > src/mem/mem_object.cc fa77985a87c6 > src/mem/port.hh fa77985a87c6 > src/mem/port.cc fa77985a87c6 > src/mem/ruby/system/RubyPort.hh fa77985a87c6 > src/mem/ruby/system/RubyPort.cc fa77985a87c6 > src/mem/simple_mem.hh fa77985a87c6 > src/mem/simple_mem.cc fa77985a87c6 > src/python/swig/pyobject.cc fa77985a87c6 > src/sim/system.hh fa77985a87c6 > src/sim/system.cc fa77985a87c6 > src/sim/tlb.hh fa77985a87c6 > > Diff: http://reviews.gem5.org/r/1273/diff/ > > > Testing > ------- > > util/regress all passing (disregarding t1000 and eio) > > > Thanks, > > Andreas Hansson > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
