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Tony... this looks great, thanks! I didn't scrutinize it as carefully as Ali did, but it looks like a lot of good fixes. Just a couple minor things I noticed before committing. src/cpu/base.cc <http://reviews.gem5.org/r/1221/#comment3360> This fancy footwork with the cpuId value deserves a comment, I think... src/python/m5/simulate.py <http://reviews.gem5.org/r/1221/#comment3361> This looks valuable for debugging, but is it output we always want to leave on? Don't we have a DPRINTF equivalent in Python? - Steve Reinhardt On Aug. 2, 2012, 2:35 p.m., Anthony Gutierrez wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/1221/ > ----------------------------------------------------------- > > (Updated Aug. 2, 2012, 2:35 p.m.) > > > Review request for Default. > > > Description > ------- > > Changeset 9139:65fc52d74391 > --------------------------- > O3,ARM: fix some problems with drain/switchout functionality and add Drain > DPRINTFs > > This patch fixes some problems with the drain/switchout functionality > for the O3 cpu and for the ARM ISA and adds some useful debug print > statements. > > This is an incremental fix as there are still a few bugs/mem leaks with the > switchout code. Particularly when switching from an O3CPU to a > TimingSimpleCPU. However, when switching from O3 to O3 cores with the ARM ISA > I haven't encountered any more assertion failures; now the kernel will > typically panic inside of simulation. > > > Diffs > ----- > > src/arch/arm/table_walker.hh b4d0bdb5269420e4675d0aceff6f1392094a73f1 > src/arch/arm/table_walker.cc b4d0bdb5269420e4675d0aceff6f1392094a73f1 > src/cpu/base.cc b4d0bdb5269420e4675d0aceff6f1392094a73f1 > src/cpu/o3/commit_impl.hh b4d0bdb5269420e4675d0aceff6f1392094a73f1 > src/cpu/o3/cpu.cc b4d0bdb5269420e4675d0aceff6f1392094a73f1 > src/cpu/o3/fetch_impl.hh b4d0bdb5269420e4675d0aceff6f1392094a73f1 > src/cpu/o3/lsq_unit.hh b4d0bdb5269420e4675d0aceff6f1392094a73f1 > src/cpu/simple/timing.cc b4d0bdb5269420e4675d0aceff6f1392094a73f1 > src/dev/copy_engine.cc b4d0bdb5269420e4675d0aceff6f1392094a73f1 > src/dev/dma_device.cc b4d0bdb5269420e4675d0aceff6f1392094a73f1 > src/dev/i8254xGBe.cc b4d0bdb5269420e4675d0aceff6f1392094a73f1 > src/mem/bus.cc b4d0bdb5269420e4675d0aceff6f1392094a73f1 > src/mem/cache/base.cc b4d0bdb5269420e4675d0aceff6f1392094a73f1 > src/mem/packet_queue.cc b4d0bdb5269420e4675d0aceff6f1392094a73f1 > src/mem/port.hh b4d0bdb5269420e4675d0aceff6f1392094a73f1 > src/mem/port.cc b4d0bdb5269420e4675d0aceff6f1392094a73f1 > src/mem/ruby/system/RubyPort.cc b4d0bdb5269420e4675d0aceff6f1392094a73f1 > src/python/m5/simulate.py b4d0bdb5269420e4675d0aceff6f1392094a73f1 > src/sim/SConscript b4d0bdb5269420e4675d0aceff6f1392094a73f1 > > Diff: http://reviews.gem5.org/r/1221/diff/ > > > Testing > ------- > > > Thanks, > > Anthony Gutierrez > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
