> On Aug. 8, 2012, 11:24 a.m., Steve Reinhardt wrote: > > src/python/m5/simulate.py, line 174 > > <http://reviews.gem5.org/r/1221/diff/9/?file=28461#file28461line174> > > > > This looks valuable for debugging, but is it output we always want to > > leave on? Don't we have a DPRINTF equivalent in Python? > > Anthony Gutierrez wrote: > I'll look into this.
I just removed it. - Anthony ----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/1221/#review3235 ----------------------------------------------------------- On Aug. 8, 2012, 9:17 p.m., Anthony Gutierrez wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/1221/ > ----------------------------------------------------------- > > (Updated Aug. 8, 2012, 9:17 p.m.) > > > Review request for Default. > > > Description > ------- > > Changeset 9148:46b12c142135 > --------------------------- > O3,ARM: fix some problems with drain/switchout functionality and add Drain > DPRINTFs > > This patch fixes some problems with the drain/switchout functionality > for the O3 cpu and for the ARM ISA and adds some useful debug print > statements. > > This is an incremental fix as there are still a few bugs/mem leaks with the > switchout code. Particularly when switching from an O3CPU to a > TimingSimpleCPU. However, when switching from O3 to O3 cores with the ARM ISA > I haven't encountered any more assertion failures; now the kernel will > typically panic inside of simulation. > > > Diffs > ----- > > src/arch/arm/table_walker.hh 05137f17887eec174fc7706ebe6295992636b8dc > src/arch/arm/table_walker.cc 05137f17887eec174fc7706ebe6295992636b8dc > src/cpu/base.cc 05137f17887eec174fc7706ebe6295992636b8dc > src/cpu/o3/commit_impl.hh 05137f17887eec174fc7706ebe6295992636b8dc > src/cpu/o3/cpu.cc 05137f17887eec174fc7706ebe6295992636b8dc > src/cpu/o3/fetch_impl.hh 05137f17887eec174fc7706ebe6295992636b8dc > src/cpu/o3/lsq_unit.hh 05137f17887eec174fc7706ebe6295992636b8dc > src/cpu/simple/timing.cc 05137f17887eec174fc7706ebe6295992636b8dc > src/dev/copy_engine.cc 05137f17887eec174fc7706ebe6295992636b8dc > src/dev/dma_device.cc 05137f17887eec174fc7706ebe6295992636b8dc > src/dev/i8254xGBe.cc 05137f17887eec174fc7706ebe6295992636b8dc > src/mem/bus.cc 05137f17887eec174fc7706ebe6295992636b8dc > src/mem/cache/base.cc 05137f17887eec174fc7706ebe6295992636b8dc > src/mem/packet_queue.cc 05137f17887eec174fc7706ebe6295992636b8dc > src/mem/port.hh 05137f17887eec174fc7706ebe6295992636b8dc > src/mem/port.cc 05137f17887eec174fc7706ebe6295992636b8dc > src/mem/ruby/system/RubyPort.cc 05137f17887eec174fc7706ebe6295992636b8dc > src/sim/SConscript 05137f17887eec174fc7706ebe6295992636b8dc > > Diff: http://reviews.gem5.org/r/1221/diff/ > > > Testing > ------- > > > Thanks, > > Anthony Gutierrez > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
