> On Aug. 8, 2012, 10:36 p.m., Steve Reinhardt wrote: > > src/cpu/base.cc, line 389 > > <http://reviews.gem5.org/r/1221/diff/13/?file=28764#file28764line389> > > > > I suggest adding this: > > > > assert(_cpuId == oldCpu->cpuId()); > > > > > > Anthony Gutierrez wrote: > I added this. It still works as well as it did before (with my > Simulation.py patch), i.e., I can boot the ALPHA kernel with a switch > frequency of 5 billion ticks. There are still kernel panics occasionally for > all ISAs. But, it's much more stable than it was before this patch. > > Nilay Vaish wrote: > Can you try with x86 as well?
It was tested on x86. Doesn't break anything and makes switching more stable. The only x86 specific problem I encountered (actually the only non-ARM ISA specific problem) was the one I addressed in this changeset: http://repo.gem5.org/gem5/rev/cc47e11ccec1 - Anthony ----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/1221/#review3246 ----------------------------------------------------------- On Aug. 9, 2012, 7:07 a.m., Anthony Gutierrez wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/1221/ > ----------------------------------------------------------- > > (Updated Aug. 9, 2012, 7:07 a.m.) > > > Review request for Default. > > > Description > ------- > > Changeset 9148:4c0189120c02 > --------------------------- > O3,ARM: fix some problems with drain/switchout functionality and add Drain > DPRINTFs > > This patch fixes some problems with the drain/switchout functionality > for the O3 cpu and for the ARM ISA and adds some useful debug print > statements. > > This is an incremental fix as there are still a few bugs/mem leaks with the > switchout code. Particularly when switching from an O3CPU to a > TimingSimpleCPU. However, when switching from O3 to O3 cores with the ARM ISA > I haven't encountered any more assertion failures; now the kernel will > typically panic inside of simulation. > > > Diffs > ----- > > src/arch/arm/table_walker.hh 05137f17887eec174fc7706ebe6295992636b8dc > src/arch/arm/table_walker.cc 05137f17887eec174fc7706ebe6295992636b8dc > src/cpu/base.cc 05137f17887eec174fc7706ebe6295992636b8dc > src/cpu/o3/commit_impl.hh 05137f17887eec174fc7706ebe6295992636b8dc > src/cpu/o3/cpu.cc 05137f17887eec174fc7706ebe6295992636b8dc > src/cpu/o3/fetch_impl.hh 05137f17887eec174fc7706ebe6295992636b8dc > src/cpu/o3/lsq_unit.hh 05137f17887eec174fc7706ebe6295992636b8dc > src/cpu/simple/timing.cc 05137f17887eec174fc7706ebe6295992636b8dc > src/dev/copy_engine.cc 05137f17887eec174fc7706ebe6295992636b8dc > src/dev/dma_device.cc 05137f17887eec174fc7706ebe6295992636b8dc > src/dev/i8254xGBe.cc 05137f17887eec174fc7706ebe6295992636b8dc > src/mem/bus.cc 05137f17887eec174fc7706ebe6295992636b8dc > src/mem/cache/base.cc 05137f17887eec174fc7706ebe6295992636b8dc > src/mem/packet_queue.cc 05137f17887eec174fc7706ebe6295992636b8dc > src/mem/port.hh 05137f17887eec174fc7706ebe6295992636b8dc > src/mem/port.cc 05137f17887eec174fc7706ebe6295992636b8dc > src/mem/ruby/system/RubyPort.cc 05137f17887eec174fc7706ebe6295992636b8dc > src/sim/SConscript 05137f17887eec174fc7706ebe6295992636b8dc > > Diff: http://reviews.gem5.org/r/1221/diff/ > > > Testing > ------- > > > Thanks, > > Anthony Gutierrez > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
