changeset 43da8ae0f36e in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=43da8ae0f36e
description:
Ruby Memory Controller: Fix clocking
diffstat:
src/mem/ruby/system/MemoryControl.cc | 2 +-
src/mem/ruby/system/MemoryControl.hh | 11 ++++++++---
src/mem/ruby/system/MemoryControl.py | 6 ++----
src/mem/ruby/system/RubyMemoryControl.cc | 15 +++++++--------
src/mem/ruby/system/RubyMemoryControl.hh | 1 -
src/mem/ruby/system/RubyMemoryControl.py | 2 ++
6 files changed, 20 insertions(+), 17 deletions(-)
diffs (142 lines):
diff -r 42807286d6cb -r 43da8ae0f36e src/mem/ruby/system/MemoryControl.cc
--- a/src/mem/ruby/system/MemoryControl.cc Tue Aug 28 17:57:51 2012 -0500
+++ b/src/mem/ruby/system/MemoryControl.cc Wed Sep 05 20:51:41 2012 -0500
@@ -42,7 +42,7 @@
#include "mem/ruby/system/System.hh"
using namespace std;
-MemoryControl::MemoryControl(const Params *p) : SimObject(p), m_event(this)
+MemoryControl::MemoryControl(const Params *p) : ClockedObject(p), m_event(this)
{
g_system_ptr->registerMemController(this);
}
diff -r 42807286d6cb -r 43da8ae0f36e src/mem/ruby/system/MemoryControl.hh
--- a/src/mem/ruby/system/MemoryControl.hh Tue Aug 28 17:57:51 2012 -0500
+++ b/src/mem/ruby/system/MemoryControl.hh Wed Sep 05 20:51:41 2012 -0500
@@ -34,24 +34,29 @@
#include <list>
#include <string>
+#include "mem/protocol/MemoryControlRequestType.hh"
#include "mem/protocol/MemoryMsg.hh"
-#include "mem/protocol/MemoryControlRequestType.hh"
#include "mem/ruby/common/Consumer.hh"
#include "mem/ruby/profiler/MemCntrlProfiler.hh"
#include "mem/ruby/slicc_interface/Message.hh"
#include "mem/ruby/system/AbstractMemOrCache.hh"
#include "mem/ruby/system/MemoryNode.hh"
#include "mem/ruby/system/System.hh"
-#include "sim/sim_object.hh"
+#include "params/MemoryControl.hh"
+#include "sim/clocked_object.hh"
//////////////////////////////////////////////////////////////////////////////
class Consumer;
class MemoryControl :
- public SimObject, public Consumer, public AbstractMemOrCache
+ public ClockedObject, public Consumer, public AbstractMemOrCache
{
public:
+ typedef MemoryControlParams Params;
+ const Params *params() const
+ { return dynamic_cast<const Params *>(_params); }
+
MemoryControl(const Params *p);
virtual void init() = 0;
virtual void reset() = 0;
diff -r 42807286d6cb -r 43da8ae0f36e src/mem/ruby/system/MemoryControl.py
--- a/src/mem/ruby/system/MemoryControl.py Tue Aug 28 17:57:51 2012 -0500
+++ b/src/mem/ruby/system/MemoryControl.py Wed Sep 05 20:51:41 2012 -0500
@@ -28,13 +28,11 @@
# Brad Beckmann
from m5.params import *
-from m5.SimObject import SimObject
+from ClockedObject import ClockedObject
-class MemoryControl(SimObject):
+class MemoryControl(ClockedObject):
abstract = True
type = 'MemoryControl'
cxx_class = 'MemoryControl'
version = Param.Int("");
ruby_system = Param.RubySystem("")
-
- mem_bus_cycle_multiplier = Param.Int(10, "");
diff -r 42807286d6cb -r 43da8ae0f36e src/mem/ruby/system/RubyMemoryControl.cc
--- a/src/mem/ruby/system/RubyMemoryControl.cc Tue Aug 28 17:57:51 2012 -0500
+++ b/src/mem/ruby/system/RubyMemoryControl.cc Wed Sep 05 20:51:41 2012 -0500
@@ -149,7 +149,6 @@
RubyMemoryControl::RubyMemoryControl(const Params *p)
: MemoryControl(p)
{
- m_mem_bus_cycle_multiplier = p->mem_bus_cycle_multiplier;
m_banks_per_rank = p->banks_per_rank;
m_ranks_per_dimm = p->ranks_per_dimm;
m_dimms_per_channel = p->dimms_per_channel;
@@ -309,7 +308,7 @@
m_input_queue.push_back(memRef);
if (!m_event.scheduled()) {
- schedule(m_event, curTick() + 1);
+ schedule(m_event, nextCycle());
}
}
@@ -377,17 +376,17 @@
void
RubyMemoryControl::enqueueToDirectory(MemoryNode req, int latency)
{
- Time arrival_time = g_system_ptr->getTime()
- + (latency * m_mem_bus_cycle_multiplier);
- req.m_time = arrival_time;
+ Time arrival_time = curTick() + (latency * clock);
+ Time ruby_arrival_time = arrival_time / g_system_ptr->getClock();
+ req.m_time = ruby_arrival_time;
m_response_queue.push_back(req);
DPRINTF(RubyMemory, "Enqueueing msg %#08x %c back to directory at %15d\n",
req.m_addr, req.m_is_mem_read ? 'R':'W',
- arrival_time * g_system_ptr->getClock());
+ arrival_time);
// schedule the wake up
- m_consumer_ptr->scheduleEventAbsolute(arrival_time);
+ m_consumer_ptr->scheduleEventAbsolute(ruby_arrival_time);
}
// getBank returns an integer that is unique for each
@@ -705,7 +704,7 @@
m_idleCount--;
if (m_idleCount > 0) {
assert(!m_event.scheduled());
- schedule(m_event, curTick() + m_mem_bus_cycle_multiplier);
+ schedule(m_event, curTick() + clock);
}
}
diff -r 42807286d6cb -r 43da8ae0f36e src/mem/ruby/system/RubyMemoryControl.hh
--- a/src/mem/ruby/system/RubyMemoryControl.hh Tue Aug 28 17:57:51 2012 -0500
+++ b/src/mem/ruby/system/RubyMemoryControl.hh Wed Sep 05 20:51:41 2012 -0500
@@ -116,7 +116,6 @@
std::string m_description;
int m_msg_counter;
- int m_mem_bus_cycle_multiplier;
int m_banks_per_rank;
int m_ranks_per_dimm;
int m_dimms_per_channel;
diff -r 42807286d6cb -r 43da8ae0f36e src/mem/ruby/system/RubyMemoryControl.py
--- a/src/mem/ruby/system/RubyMemoryControl.py Tue Aug 28 17:57:51 2012 -0500
+++ b/src/mem/ruby/system/RubyMemoryControl.py Wed Sep 05 20:51:41 2012 -0500
@@ -36,6 +36,8 @@
cxx_class = 'RubyMemoryControl'
version = Param.Int("");
+ # Override the default clock
+ clock = '400MHz'
banks_per_rank = Param.Int(8, "");
ranks_per_dimm = Param.Int(2, "");
dimms_per_channel = Param.Int(2, "");
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