changeset dfc6a4ba338c in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=dfc6a4ba338c
description:
se.py Ruby: Connect TLB walker ports
In order to ensure correct functionality of switch CPUs, the TLB walker
ports
must be connected to the Ruby system in x86 simulation.
This fixes x86 assertion failures that the TLB walker ports are not
connected
during the CPU switch process.
diffstat:
configs/example/se.py | 3 +++
1 files changed, 3 insertions(+), 0 deletions(-)
diffs (13 lines):
diff -r 4f54b0f229b5 -r dfc6a4ba338c configs/example/se.py
--- a/configs/example/se.py Wed Sep 12 21:41:37 2012 -0500
+++ b/configs/example/se.py Wed Sep 12 21:42:57 2012 -0500
@@ -198,6 +198,9 @@
# Connect the cpu's cache ports to Ruby
system.cpu[i].icache_port = ruby_port.slave
system.cpu[i].dcache_port = ruby_port.slave
+ if buildEnv['TARGET_ISA'] == 'x86':
+ system.cpu[i].itb.walker.port = ruby_port.slave
+ system.cpu[i].dtb.walker.port = ruby_port.slave
else:
system.system_port = system.membus.slave
system.physmem.port = system.membus.master
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