> On Sept. 12, 2012, 9:44 a.m., Ali Saidi wrote: > > src/mem/SimpleMemory.py, line 50 > > <http://reviews.gem5.org/r/1416/diff/1/?file=29686#file29686line50> > > > > do we at least want to put this in the land of reasonable? 16GB/s? > > > > Andreas Hansson wrote: > I merely kept it at this value to not affect any regression. It could > probably be smaller and still be fine. I'll do some binary searching. > > Andreas Hansson wrote: > My suggestion is to get this patch committed, then have a separate patch > that reduces this value to something reasonable along the lines of 8GB/s or > 16GB/s (any opinions here?) and also go through the FSConfig.py, se.py, > fs.py, tests/config/*.py and choose some more-or-less educated defaults for > the various systems. I would be keen to hear what you guys think it should be. > > 4GB/s for all arm/mips? 8GB/s for x86/alpha/sparc? power? > > Ali Saidi wrote: > we don't need a different version for different architectures... just > pick one. > > Andreas Hansson wrote: > Would a default of 8GB/s be ok with everyone? That way I only have to set > a single parameter. > > I can run a full regression and bump the stats tonight. > > Andreas Hansson wrote: > I've now set it to 12.8GB/s which matches a x64 DDR3-1600 channel. I'll > make that change part of this patch, and then bump the stats in a separate > patch following it (unless anyone disagrees).
I've now got a patch also for the update of the stats using a 12.8GB/s limit. Are you happy to ship this Ali? - Andreas ----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/1416/#review3453 ----------------------------------------------------------- On Sept. 12, 2012, 9:48 a.m., Andreas Hansson wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/1416/ > ----------------------------------------------------------- > > (Updated Sept. 12, 2012, 9:48 a.m.) > > > Review request for Default. > > > Description > ------- > > Changeset 9220:8ae1bebee1ea > --------------------------- > Mem: Add a maximum bandwidth to SimpleMemory > > This patch makes a minor addition to the SimpleMemory by enforcing a > maximum data rate. The bandwidth is configurable, and a sizeable value > (1PB/s) has been choosen as the default to not upset any regressions > or existing systems. > > The changes do add some complexity to the SimpleMemory, but they > should definitely be justifiable as this enables a far more realistic > setup using even this simple memory controller. > > The rate regulation is done for reads and writes combined to reflect > the bidirectional data busses used by most (if not all) relevant > memories. Moreover, the regulation is done per packet as opposed to > long term, as it is the short term data rate (data bus width times > frequency) that is the limiting factor. > > In a follow-up patch it would be reasonable to go through the default > system configurations and choose realistic values for the memory > bandwidth. Currently the default is 1PB/s to effectively disable the > limit. > > > Diffs > ----- > > src/mem/SimpleMemory.py d3772fe85fa6 > src/mem/simple_mem.hh d3772fe85fa6 > src/mem/simple_mem.cc d3772fe85fa6 > > Diff: http://reviews.gem5.org/r/1416/diff/ > > > Testing > ------- > > util/regress all passing (disregarding t1000 and eio) > > > Thanks, > > Andreas Hansson > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
