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Review request for Default. Description ------- Changeset 9220:1e6e9d3b75c2 --------------------------- Mem: Add a maximum bandwidth to SimpleMemory This patch makes a minor addition to the SimpleMemory by enforcing a maximum data rate. The bandwidth is configurable, and a sizeable value (1PB/s) has been choosen as the default to not upset any regressions or existing systems. The changes do add some complexity to the SimpleMemory, but they should definitely be justifiable as this enables a far more realistic setup using even this simple memory controller. The rate regulation is done for reads and writes combined to reflect the bidirectional data busses used by most (if not all) relevant memories. Moreover, the regulation is done per packet as opposed to long term, as it is the short term data rate (data bus width times frequency) that is the limiting factor. In a follow-up patch it would be reasonable to go through the default system configurations and choose realistic values for the memory bandwidth. Currently the default is 1PB/s to effectively disable the limit. Diffs ----- src/mem/SimpleMemory.py d3772fe85fa6 src/mem/simple_mem.hh d3772fe85fa6 src/mem/simple_mem.cc d3772fe85fa6 Diff: http://reviews.gem5.org/r/1416/diff/ Testing ------- util/regress all passing (disregarding t1000 and eio) Thanks, Andreas Hansson _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
