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Ship it! Ship It! - Nilay Vaish On Sept. 28, 2012, 6:19 a.m., Andreas Hansson wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/1452/ > ----------------------------------------------------------- > > (Updated Sept. 28, 2012, 6:19 a.m.) > > > Review request for Default. > > > Description > ------- > > changesets: > 9276:ef6840cfba82 "Configs: Set the memtest clock to a reasonable value > > This patch changes the memtest clock from 1THz (the default) to 2GHz, > similar to the CPUs in the other regressions. This is useful as the > caches will adopt the same clock as the CPU. The bus clock rate is > scaled accordingly, and the L1-L2 bus is kept at the CPU clock while > the memory bus is at half that frequency. > > A separate patch updates the affected stats." > > > Diffs > ----- > > tests/configs/memtest-ruby.py f8c85a7d109f > tests/configs/memtest.py f8c85a7d109f > > Diff: http://reviews.gem5.org/r/1452/diff/ > > > Testing > ------- > > > Thanks, > > Andreas Hansson > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
