> On Sept. 28, 2012, 12:15 p.m., Anthony Gutierrez wrote: > > configs/common/O3_ARM_v7a.py, line 199 > > <http://reviews.gem5.org/r/1453/diff/1/?file=29971#file29971line199> > > > > Can you make the Prefetcher and this config based on cycles as well?
Well spotted. Will do so and repost. - Andreas ----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/1453/#review3541 ----------------------------------------------------------- On Sept. 28, 2012, 7:04 a.m., Andreas Hansson wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/1453/ > ----------------------------------------------------------- > > (Updated Sept. 28, 2012, 7:04 a.m.) > > > Review request for Default. > > > Description > ------- > > changesets: > 9278:5632789a09c1 "Mem: Use cycles to express cache-related latencies > > This patch changes the cache-related latencies from an absolute time > expressed in Ticks, to a number of cycles that can be scaled with the > clock period of the caches. Ultimately this patch serves to enable > future work that involves dynamic frequency scaling. As an immediate > benefit it also makes it more convenient to specify cache performance > without implicitly assuming a specific CPU core operating frequency. > > The stat blocked_cycles that actually counter in ticks is now updated > to count in cycles. > > As the timing is now rounded to the clock edges of the cache, there > are some regressions that change. Plenty of them have very minor > changes, whereas some regressions with a short run-time are perturbed > quite significantly. A follow-on patch updates all the statistics for > the regressions." > > > Diffs > ----- > > configs/common/Caches.py f8c85a7d109f > configs/common/O3_ARM_v7a.py f8c85a7d109f > src/mem/cache/BaseCache.py f8c85a7d109f > src/mem/cache/base.hh f8c85a7d109f > src/mem/cache/base.cc f8c85a7d109f > src/mem/cache/cache.hh f8c85a7d109f > src/mem/cache/cache_impl.hh f8c85a7d109f > src/mem/cache/tags/fa_lru.hh f8c85a7d109f > src/mem/cache/tags/fa_lru.cc f8c85a7d109f > src/mem/cache/tags/iic.hh f8c85a7d109f > src/mem/cache/tags/iic.cc f8c85a7d109f > src/mem/cache/tags/lru.hh f8c85a7d109f > src/mem/cache/tags/lru.cc f8c85a7d109f > tests/configs/inorder-timing.py f8c85a7d109f > tests/configs/memtest.py f8c85a7d109f > tests/configs/o3-timing-checker.py f8c85a7d109f > tests/configs/o3-timing-mp.py f8c85a7d109f > tests/configs/o3-timing.py f8c85a7d109f > tests/configs/pc-o3-timing.py f8c85a7d109f > tests/configs/pc-simple-atomic.py f8c85a7d109f > tests/configs/pc-simple-timing.py f8c85a7d109f > tests/configs/realview-o3-checker.py f8c85a7d109f > tests/configs/realview-o3-dual.py f8c85a7d109f > tests/configs/realview-o3.py f8c85a7d109f > tests/configs/realview-simple-atomic-dual.py f8c85a7d109f > tests/configs/realview-simple-atomic.py f8c85a7d109f > tests/configs/realview-simple-timing-dual.py f8c85a7d109f > tests/configs/realview-simple-timing.py f8c85a7d109f > tests/configs/simple-atomic-mp.py f8c85a7d109f > tests/configs/simple-timing-mp.py f8c85a7d109f > tests/configs/simple-timing.py f8c85a7d109f > tests/configs/tsunami-inorder.py f8c85a7d109f > tests/configs/tsunami-o3-dual.py f8c85a7d109f > tests/configs/tsunami-o3.py f8c85a7d109f > tests/configs/tsunami-simple-atomic-dual.py f8c85a7d109f > tests/configs/tsunami-simple-atomic.py f8c85a7d109f > tests/configs/tsunami-simple-timing-dual.py f8c85a7d109f > tests/configs/tsunami-simple-timing.py f8c85a7d109f > > Diff: http://reviews.gem5.org/r/1453/diff/ > > > Testing > ------- > > util/regress all passing (disregarding t1000 and eio) > > Updates to stats will follow > > > Thanks, > > Andreas Hansson > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
