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Ship it! Ship It! - Anthony Gutierrez On Oct. 11, 2012, 2:48 a.m., Andreas Hansson wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/1453/ > ----------------------------------------------------------- > > (Updated Oct. 11, 2012, 2:48 a.m.) > > > Review request for Default. > > > Description > ------- > > Changeset 9288:99535ef63467 > --------------------------- > Mem: Use cycles to express cache-related latencies > > This patch changes the cache-related latencies from an absolute time > expressed in Ticks, to a number of cycles that can be scaled with the > clock period of the caches. Ultimately this patch serves to enable > future work that involves dynamic frequency scaling. As an immediate > benefit it also makes it more convenient to specify cache performance > without implicitly assuming a specific CPU core operating frequency. > > The stat blocked_cycles that actually counter in ticks is now updated > to count in cycles. > > As the timing is now rounded to the clock edges of the cache, there > are some regressions that change. Plenty of them have very minor > changes, whereas some regressions with a short run-time are perturbed > quite significantly. A follow-on patch updates all the statistics for > the regressions. > > > Diffs > ----- > > configs/common/Caches.py a5ede748a1d9 > configs/common/O3_ARM_v7a.py a5ede748a1d9 > src/mem/cache/BaseCache.py a5ede748a1d9 > src/mem/cache/base.hh a5ede748a1d9 > src/mem/cache/base.cc a5ede748a1d9 > src/mem/cache/cache.hh a5ede748a1d9 > src/mem/cache/cache_impl.hh a5ede748a1d9 > src/mem/cache/prefetch/Prefetcher.py a5ede748a1d9 > src/mem/cache/prefetch/base.hh a5ede748a1d9 > src/mem/cache/prefetch/base.cc a5ede748a1d9 > src/mem/cache/prefetch/ghb.hh a5ede748a1d9 > src/mem/cache/prefetch/ghb.cc a5ede748a1d9 > src/mem/cache/prefetch/stride.hh a5ede748a1d9 > src/mem/cache/prefetch/stride.cc a5ede748a1d9 > src/mem/cache/prefetch/tagged.hh a5ede748a1d9 > src/mem/cache/prefetch/tagged.cc a5ede748a1d9 > src/mem/cache/tags/fa_lru.hh a5ede748a1d9 > src/mem/cache/tags/fa_lru.cc a5ede748a1d9 > src/mem/cache/tags/iic.hh a5ede748a1d9 > src/mem/cache/tags/iic.cc a5ede748a1d9 > src/mem/cache/tags/lru.hh a5ede748a1d9 > src/mem/cache/tags/lru.cc a5ede748a1d9 > tests/configs/inorder-timing.py a5ede748a1d9 > tests/configs/memtest.py a5ede748a1d9 > tests/configs/o3-timing-checker.py a5ede748a1d9 > tests/configs/o3-timing-mp.py a5ede748a1d9 > tests/configs/o3-timing.py a5ede748a1d9 > tests/configs/pc-o3-timing.py a5ede748a1d9 > tests/configs/pc-simple-atomic.py a5ede748a1d9 > tests/configs/pc-simple-timing.py a5ede748a1d9 > tests/configs/realview-o3-checker.py a5ede748a1d9 > tests/configs/realview-o3-dual.py a5ede748a1d9 > tests/configs/realview-o3.py a5ede748a1d9 > tests/configs/realview-simple-atomic-dual.py a5ede748a1d9 > tests/configs/realview-simple-atomic.py a5ede748a1d9 > tests/configs/realview-simple-timing-dual.py a5ede748a1d9 > tests/configs/realview-simple-timing.py a5ede748a1d9 > tests/configs/simple-atomic-mp.py a5ede748a1d9 > tests/configs/simple-timing-mp.py a5ede748a1d9 > tests/configs/simple-timing.py a5ede748a1d9 > tests/configs/tsunami-inorder.py a5ede748a1d9 > tests/configs/tsunami-o3-dual.py a5ede748a1d9 > tests/configs/tsunami-o3.py a5ede748a1d9 > tests/configs/tsunami-simple-atomic-dual.py a5ede748a1d9 > tests/configs/tsunami-simple-atomic.py a5ede748a1d9 > tests/configs/tsunami-simple-timing-dual.py a5ede748a1d9 > tests/configs/tsunami-simple-timing.py a5ede748a1d9 > > Diff: http://reviews.gem5.org/r/1453/diff/ > > > Testing > ------- > > util/regress all passing (disregarding t1000 and eio) > > Updates to stats will follow > > > Thanks, > > Andreas Hansson > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
