On 01.02.2013 17:33, Nilay wrote:
> On Fri, February 1, 2013 4:13 pm, Mitch Hayenga wrote: > >> Hi all, My advisor is teaching our graduate parallel computer architecture class this semester and he has a ton of students (40+ I think). Given so many students, he is trying to find additional ideas for those students who can't come up with project ideas on their own. Often we try to make the student project results useful beyond the class. So I was wondering if any of the gem5-devs knew of places where they would like to see gem5 improvement, but the given task is too time consuming given their other tasks/objectives. These tasks should be able to be tied in with the learning that should occur in a grad comp arch class. Here are some I've come up with: 1) SE TLB latency modeling TLBs lookups in SE mode respond immediately. Modify this behavior to properly model lookup latency. A simple class project could be doing this in addition to trying to make/model TLB prefetchers, but the main benefit would be SE TLB latency modeling. 2) Gem5 Classic Coherence Modify the coherence protocol in gem5-classic to behave more as you would expect a MOESI protocol to. I've posted myself on this previously ( http://www.mail-archive.com/gem5-users@gem5.org/msg01021.html [1]). They could also try to extend the protocol. 3) Extended prefetchers Add more complicated/intelligent prefetchers to gem5. 4) Loop buffer modeling/prediction in O3 Any other places where a minor issue exists, you lack the time to fix it, and you think it could make a good parallel computer architecture class project? > > Some things from my todo list -- > > 1. support for smt in x86 architecture > 2. three level coherence protocol in ruby > 3. verifying coherence protocol / memory model > 4. inorder cpu for x86 > 5. better branch prediction / prefetch algorithms. > > -- > Nilay > > _______________________________________________ > gem5-dev mailing list > gem5-dev@gem5.org > http://m5sim.org/mailman/listinfo/gem5-dev [2] 1. HW Prefetching (different pre-fetchers, ones that work better, handing priority through the entire memory system) 2. SW prefetching, currently we do a bad job of this in the pipeline (it can stall at the head) and exposing the fact that it's a prefetch to the system 3. Temporal/Non-temporal loads/stores (e.g. stores that bypass layers of the caching hierarchy) 4. Support in classic memory system for write-line-unique (e.g. if the L1 cache has outstanding requests for the entire line, there is no need to do a RMW; same thing for an I/O device) Thanks, Ali Links: ------ [1] http://www.mail-archive.com/gem5-users@gem5.org/msg01021.html [2] http://m5sim.org/mailman/listinfo/gem5-dev _______________________________________________ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
