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While this seems harmless enough, I wonder if there is some interaction between faults/interrupts and the instruction that we should worry about. I haven't given it enough thought to say either way, but it seems like it could be a concern. - Ali Saidi On March 29, 2013, 7:47 p.m., Mitch Hayenga wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/1805/ > ----------------------------------------------------------- > > (Updated March 29, 2013, 7:47 p.m.) > > > Review request for Default. > > > Description > ------- > > Mark ARM IT (if-then) instructions as nops. > > ARM's IT instructions predicate up to the next 4 instructions on various > condition codes. IT instructions really just send control signals to the > decoder, after decode they do not read or write any registers. Marking them > as nops (along with the other patch that drops nops at decode) saves > execution resources and bandwidth. > > > Diffs > ----- > > src/arch/arm/isa/insts/misc.isa 47591444a7c5 > > Diff: http://reviews.gem5.org/r/1805/diff/ > > > Testing > ------- > > A fast libquantum run. > > > Thanks, > > Mitch Hayenga > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
