I'm implementing a cache bank model, and in some cases, I need to block the
response packet, e.g. cache miss -> DDR read -> DDR read response return to
cache (cache line fill) -> cache bank is busy and cache line fill has to be
delayed
However, I got some difficulties in implementing this feature. The main
problem is that the CoherentBus.cc does not support to block responses. I
saw code/comment in CoherentBus.cc like:
// currently it is illegal to block responses... can lead to
// deadlock
assert(success);
in CoherentBus::recvTimingResp()
So, I want to ask if this limitation still exists. If so, any idea to
bypass it?
Thank you!
Best,
Xiangyu
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