Hi Andreas,

Thank you for your input.  I'm afraid approach #1 does not work in my case
as the data requester is not able to predict when the data will return and
whether the requester itself will be busy or not when the data returns.  So,
I think I will do approach #2.  I will first try to understand how the gem5
bus model works.  Of course, your help will be very appreciated.

Best,
Xiangyu

-----Original Message-----
From: [email protected] [mailto:[email protected]] On Behalf
Of Andreas Hansson
Sent: Monday, April 15, 2013 2:43 PM
To: gem5 Developer List
Subject: Re: [gem5-dev] Illegal to block responses

Hi Xiangyu,

The limitation is still there, but would be easy to remove. It stems from
the fact that all modules ensure that they are ready to accept the response
before issuing the corresponding request. Thus, you can either:

1) block the request (not sure this would work in your case)

2) enhance the bus to do the same level of flow control for responses as it
does for requests (I can probably help with the latter)

Andreas

On 15/04/2013 21:59, "Rio Xiangyu Dong" <[email protected]> wrote:

>I'm implementing a cache bank model, and in some cases, I need to block 
>the response packet, e.g. cache miss -> DDR read -> DDR read response 
>return to cache (cache line fill) -> cache bank is busy and cache line 
>fill has to be delayed
>
>
>
>However, I got some difficulties in implementing this feature.  The 
>main problem is that the CoherentBus.cc does not support to block 
>responses.  I saw code/comment in CoherentBus.cc like:
>
>    // currently it is illegal to block responses... can lead to
>
>    // deadlock
>
>assert(success);
>
>in CoherentBus::recvTimingResp()
>
>
>
>So, I want to ask if this limitation still exists.  If so, any idea to 
>bypass it?
>
>
>
>Thank you!
>
>
>
>Best,
>
>Xiangyu
>
>_______________________________________________
>gem5-dev mailing list
>[email protected]
>http://m5sim.org/mailman/listinfo/gem5-dev
>


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