changeset d35bd171cf2a in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=d35bd171cf2a
description:
x86: regressions: add switcher full test
diffstat:
tests/SConscript
| 3 +-
tests/configs/base_config.py
| 16 +-
tests/configs/pc-switcheroo-full.py
| 50 +
tests/configs/x86_generic.py
| 8 +
tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.ini
| 1594 ++++++++++
tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simerr
| 15 +
tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simout
| 12 +
tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt
| 1332 ++++++++
tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/system.pc.com_1.terminal
| 137 +
9 files changed, 3157 insertions(+), 10 deletions(-)
diffs (truncated from 3233 to 300 lines):
diff -r 3885582ecc52 -r d35bd171cf2a tests/SConscript
--- a/tests/SConscript Tue Apr 23 00:03:07 2013 -0500
+++ b/tests/SConscript Tue Apr 23 00:03:09 2013 -0500
@@ -323,7 +323,8 @@
if env['TARGET_ISA'] == 'x86':
configs += ['pc-simple-atomic',
'pc-simple-timing',
- 'pc-o3-timing']
+ 'pc-o3-timing',
+ 'pc-switcheroo-full']
configs += ['simple-atomic', 'simple-timing', 'o3-timing', 'memtest',
'simple-atomic-mp', 'simple-timing-mp', 'o3-timing-mp',
diff -r 3885582ecc52 -r d35bd171cf2a tests/configs/base_config.py
--- a/tests/configs/base_config.py Tue Apr 23 00:03:07 2013 -0500
+++ b/tests/configs/base_config.py Tue Apr 23 00:03:09 2013 -0500
@@ -104,14 +104,18 @@
system.l2c.mem_side = system.membus.slave
return system.toL2Bus
- def init_cpu(self, system, cpu):
+ def init_cpu(self, system, cpu, sha_bus):
"""Initialize a CPU.
Arguments:
system -- System to work on.
cpu -- CPU to initialize.
"""
- cpu.createInterruptController()
+ if not cpu.switched_out:
+ self.create_caches_private(cpu)
+ cpu.createInterruptController()
+ cpu.connectAllPorts(sha_bus if sha_bus != None else system.membus,
+ system.membus)
def init_kvm(self, system):
"""Do KVM-specific system initialization.
@@ -135,13 +139,7 @@
sha_bus = self.create_caches_shared(system)
for cpu in system.cpu:
- if not cpu.switched_out:
- self.create_caches_private(cpu)
- self.init_cpu(system, cpu)
- cpu.connectAllPorts(sha_bus if sha_bus != None else
system.membus,
- system.membus)
- else:
- self.init_cpu(system, cpu)
+ self.init_cpu(system, cpu, sha_bus)
@abstractmethod
def create_system(self):
diff -r 3885582ecc52 -r d35bd171cf2a tests/configs/pc-switcheroo-full.py
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/tests/configs/pc-switcheroo-full.py Tue Apr 23 00:03:09 2013 -0500
@@ -0,0 +1,50 @@
+# Copyright (c) 2012 ARM Limited
+# Copyright (c) 2013 Mark D. Hill and David A. Wood
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder. You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Andreas Sandberg
+# Nilay Vaish
+
+from m5.objects import *
+from x86_generic import *
+import switcheroo
+
+root = LinuxX86FSSwitcheroo(
+ cpu_classes=(AtomicSimpleCPU, TimingSimpleCPU, DerivO3CPU)
+ ).create_root()
+
+# Setup a custom test method that uses the switcheroo tester that
+# switches between CPU models.
+run_test = switcheroo.run_test
diff -r 3885582ecc52 -r d35bd171cf2a tests/configs/x86_generic.py
--- a/tests/configs/x86_generic.py Tue Apr 23 00:03:07 2013 -0500
+++ b/tests/configs/x86_generic.py Tue Apr 23 00:03:09 2013 -0500
@@ -107,3 +107,11 @@
L2Cache(size='4MB', assoc=8),
PageTableWalkerCache(),
PageTableWalkerCache())
+
+
+class LinuxX86FSSwitcheroo(LinuxX86SystemBuilder, BaseFSSwitcheroo):
+ """Uniprocessor X86 system prepared for CPU switching"""
+
+ def __init__(self, **kwargs):
+ BaseFSSwitcheroo.__init__(self, **kwargs)
+ LinuxX86SystemBuilder.__init__(self)
diff -r 3885582ecc52 -r d35bd171cf2a
tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.ini
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.ini
Tue Apr 23 00:03:09 2013 -0500
@@ -0,0 +1,1594 @@
+[root]
+type=Root
+children=system
+full_system=true
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=LinuxX86System
+children=acpi_description_table_pointer apicbridge bridge cpu0 cpu1 cpu2
e820_table intel_mp_pointer intel_mp_table intrctrl iobus iocache l2c membus pc
physmem smbios_table toL2Bus
+acpi_description_table_pointer=system.acpi_description_table_pointer
+boot_osflags=earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1
+clock=1000
+e820_table=system.e820_table
+init_param=0
+intel_mp_pointer=system.intel_mp_pointer
+intel_mp_table=system.intel_mp_table
+kernel=/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9
+load_addr_mask=18446744073709551615
+mem_mode=atomic
+mem_ranges=0:134217727
+memories=system.physmem
+num_work_ids=16
+readfile=tests/halt.sh
+smbios_table=system.smbios_table
+symbolfile=
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.slave[1]
+
+[system.acpi_description_table_pointer]
+type=X86ACPIRSDP
+children=xsdt
+oem_id=
+revision=2
+rsdt=Null
+xsdt=system.acpi_description_table_pointer.xsdt
+
+[system.acpi_description_table_pointer.xsdt]
+type=X86ACPIXSDT
+creator_id=
+creator_revision=0
+entries=
+oem_id=
+oem_revision=0
+oem_table_id=
+
+[system.apicbridge]
+type=Bridge
+clock=1000
+delay=50000
+ranges=11529215046068469760:11529215046068473855
+req_size=16
+resp_size=16
+master=system.membus.slave[0]
+slave=system.iobus.master[0]
+
+[system.bridge]
+type=Bridge
+clock=1000
+delay=50000
+ranges=4273995776:4273999871 9223372036854775808:11529215046068469759
13835058055282163712:18446744073709551615
+req_size=16
+resp_size=16
+master=system.iobus.slave[0]
+slave=system.membus.master[1]
+
+[system.cpu0]
+type=AtomicSimpleCPU
+children=dcache dtb icache interrupts isa itb tracer
+branchPred=Null
+checker=Null
+clock=500
+cpu_id=0
+do_checkpoint_insts=true
+do_quiesce=true
+do_statistics_insts=true
+dtb=system.cpu0.dtb
+fastmem=false
+function_trace=false
+function_trace_start=0
+interrupts=system.cpu0.interrupts
+isa=system.cpu0.isa
+itb=system.cpu0.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+profile=0
+progress_interval=0
+simpoint_interval=100000000
+simpoint_profile=false
+simpoint_profile_file=simpoint.bb.gz
+simpoint_start_insts=
+simulate_data_stalls=false
+simulate_inst_stalls=false
+switched_out=false
+system=system
+tracer=system.cpu0.tracer
+width=1
+workload=
+dcache_port=system.cpu0.dcache.cpu_side
+icache_port=system.cpu0.icache.cpu_side
+
+[system.cpu0.dcache]
+type=BaseCache
+addr_ranges=0:18446744073709551615
+assoc=4
+block_size=64
+clock=500
+forward_snoops=true
+hit_latency=2
+is_top_level=true
+max_miss_count=0
+mshrs=4
+prefetch_on_access=false
+prefetcher=Null
+response_latency=2
+size=32768
+system=system
+tgts_per_mshr=20
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu0.dcache_port
+mem_side=system.toL2Bus.slave[1]
+
+[system.cpu0.dtb]
+type=X86TLB
+children=walker
+size=64
+walker=system.cpu0.dtb.walker
+
+[system.cpu0.dtb.walker]
+type=X86PagetableWalker
+clock=500
+system=system
+port=system.toL2Bus.slave[3]
+
+[system.cpu0.icache]
+type=BaseCache
+addr_ranges=0:18446744073709551615
+assoc=1
+block_size=64
+clock=500
+forward_snoops=true
+hit_latency=2
+is_top_level=true
+max_miss_count=0
+mshrs=4
+prefetch_on_access=false
+prefetcher=Null
+response_latency=2
+size=32768
+system=system
+tgts_per_mshr=20
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu0.icache_port
+mem_side=system.toL2Bus.slave[0]
+
+[system.cpu0.interrupts]
+type=X86LocalApic
+clock=8000
+int_latency=1000
+pio_addr=2305843009213693952
+pio_latency=100000
+system=system
+int_master=system.membus.slave[3]
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