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Ship it! Ship It! - Anthony Gutierrez On May 11, 2013, 10:31 a.m., Andreas Hansson wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/1867/ > ----------------------------------------------------------- > > (Updated May 11, 2013, 10:31 a.m.) > > > Review request for Default. > > > Description > ------- > > Changeset 9709:655693f3a878 > --------------------------- > mem: Add static latency to the DRAM controller > > This patch adds a frontend and backend static latency to the DRAM > controller by delaying the responses. Two parameters expressing the > frontend and backend contributions in absolute time are added to the > controller, and the appropriate latency is added to the responses when > adding them to the (infinite) queued port for sending. > > For writes and reads that hit in the write buffer, only the frontend > latency is added. For reads that are serviced by the DRAM, the static > latency is the sum of the pipeline latencies of the entire frontend, > backend and PHY. The default values are chosen based on having roughly > 10 pipeline stages in total at 500 MHz. > > In the future, it would be sensible to make the controller use its > clock and convert these latencies (and a few of the DRAM timings) to > cycles. > > > Diffs > ----- > > src/mem/SimpleDRAM.py eb075b2b925a > src/mem/simple_dram.hh eb075b2b925a > src/mem/simple_dram.cc eb075b2b925a > > Diff: http://reviews.gem5.org/r/1867/diff/ > > > Testing > ------- > > All regressions pass with stats update > > > Thanks, > > Andreas Hansson > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
