----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/1947/#review4504 -----------------------------------------------------------
Seems fine to me. - Nilay Vaish On July 12, 2013, 2:04 p.m., Andreas Hansson wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/1947/ > ----------------------------------------------------------- > > (Updated July 12, 2013, 2:04 p.m.) > > > Review request for Default. > > > Repository: gem5 > > > Description > ------- > > Changeset 9813:2b4e8e368e3a > --------------------------- > mem: Add an internal packet queue in SimpleMemory > > This patch adds a packet queue in SimpleMemory to avoid using the > packet queue in the port (and thus have no involvement in the flow > control). The port queue was bound to 100 packets, and as the > SimpleMemory is modelling both a controller and an actual RAM, it > potentially has a large number of packets in flight. There is > currently no limit on the number of packets in the memory controller, > but this could easily be added in a follow-on patch. > > As a result of the added internal storage, the functional access and > draining is updated. Some minor cleaning up and renaming has also been > done. > > The memtest regression changes as a result of this patch and the stats > will be updated. > > > Diffs > ----- > > src/mem/SimpleMemory.py 13ffc0066b76 > src/mem/simple_mem.hh 13ffc0066b76 > src/mem/simple_mem.cc 13ffc0066b76 > > Diff: http://reviews.gem5.org/r/1947/diff/ > > > Testing > ------- > > All regressions pass (after updating memtest) > > > Thanks, > > Andreas Hansson > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
