In the process of adding support for a fourth class of registers (to handle condition codes more explicitly in x86), I wound up wading through a bunch of confusing register-handling code. In the process of trying to figure out what was going on, I figured I would write up some documentation, in part so that you all could look at what I think I figured out and tell me if I got it right. (Korey had done a write-up earlier on register indexing, but it wasn't totally comprehensive, so I decided to start over.)
The new page is here: http://gem5.org/Register_Indexing Please take a look and provide some feedback (or just edit the page directly), particularly if you see anything there that's not accurate. Thanks, Steve _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
