changeset 603e2ed487f3 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=603e2ed487f3
description:
cpu: Move the branch predictor out of the BaseCPU
The branch predictor is guarded by having either the in-order or
out-of-order CPU as one of the available CPU models and therefore
should not be used in the BaseCPU. This patch moves the parameter to
the relevant CPU classes.
diffstat:
src/cpu/BaseCPU.py | 3 ---
src/cpu/inorder/InOrderCPU.py | 4 +++-
src/cpu/o3/O3CPU.py | 4 +++-
3 files changed, 6 insertions(+), 5 deletions(-)
diffs (45 lines):
diff -r a733a8eb6363 -r 603e2ed487f3 src/cpu/BaseCPU.py
--- a/src/cpu/BaseCPU.py Wed Sep 04 13:22:55 2013 -0400
+++ b/src/cpu/BaseCPU.py Wed Sep 04 13:22:56 2013 -0400
@@ -51,7 +51,6 @@
from InstTracer import InstTracer
from ExeTracer import ExeTracer
from MemObject import MemObject
-from BranchPredictor import BranchPredictor
from ClockDomain import *
default_tracer = ExeTracer()
@@ -210,8 +209,6 @@
dcache_port = MasterPort("Data Port")
_cached_ports = ['icache_port', 'dcache_port']
- branchPred = Param.BranchPredictor(NULL, "Branch Predictor")
-
if buildEnv['TARGET_ISA'] in ['x86', 'arm']:
_cached_ports += ["itb.walker.port", "dtb.walker.port"]
diff -r a733a8eb6363 -r 603e2ed487f3 src/cpu/inorder/InOrderCPU.py
--- a/src/cpu/inorder/InOrderCPU.py Wed Sep 04 13:22:55 2013 -0400
+++ b/src/cpu/inorder/InOrderCPU.py Wed Sep 04 13:22:56 2013 -0400
@@ -68,4 +68,6 @@
div32Latency = Param.Cycles(1, "Latency for 32-bit Divide Operations")
div32RepeatRate = Param.Cycles(1, "Repeat Rate for 32-bit Divide
Operations")
- branchPred = BranchPredictor(numThreads = Parent.numThreads)
+ branchPred = Param.BranchPredictor(BranchPredictor(numThreads =
+ Parent.numThreads),
+ "Branch Predictor")
diff -r a733a8eb6363 -r 603e2ed487f3 src/cpu/o3/O3CPU.py
--- a/src/cpu/o3/O3CPU.py Wed Sep 04 13:22:55 2013 -0400
+++ b/src/cpu/o3/O3CPU.py Wed Sep 04 13:22:56 2013 -0400
@@ -125,7 +125,9 @@
smtROBThreshold = Param.Int(100, "SMT ROB Threshold Sharing Parameter")
smtCommitPolicy = Param.String('RoundRobin', "SMT Commit Policy")
- branchPred = BranchPredictor(numThreads = Parent.numThreads)
+ branchPred = Param.BranchPredictor(BranchPredictor(numThreads =
+ Parent.numThreads),
+ "Branch Predictor")
needsTSO = Param.Bool(buildEnv['TARGET_ISA'] == 'x86',
"Enable TSO Memory model")
_______________________________________________
gem5-dev mailing list
[email protected]
http://m5sim.org/mailman/listinfo/gem5-dev
