changeset 87d6b41749e9 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=87d6b41749e9
description:
arch: Resurrect the NOISA build target and rename it NULL
This patch makes it possible to once again build gem5 without any
ISA. The main purpose is to enable work around the interconnect and
memory system without having to build any CPU models or device models.
The regress script is updated to include the NULL ISA target. Currently
no regressions make use of it, but all the testers could (and perhaps
should) transition to it.
diffstat:
build_opts/NOISA | 2 -
build_opts/NULL | 2 +
src/arch/generic/SConscript | 3 +
src/arch/noisa/SConsopts | 4 --
src/arch/noisa/cpu_dummy.hh | 7 ----
src/arch/null/SConscript | 43 ++++++++++++++++++++++++++
src/arch/null/SConsopts | 42 +++++++++++++++++++++++++
src/arch/null/cpu_dummy.cc | 44 ++++++++++++++++++++++++++
src/arch/null/cpu_dummy.hh | 52 +++++++++++++++++++++++++++++++
src/arch/null/isa_traits.hh | 59 ++++++++++++++++++++++++++++++++++++
src/arch/null/registers.hh | 54 ++++++++++++++++++++++++++++++++
src/arch/null/remote_gdb.hh | 56 ++++++++++++++++++++++++++++++++++
src/arch/null/types.hh | 58 +++++++++++++++++++++++++++++++++++
src/arch/null/utility.hh | 55 +++++++++++++++++++++++++++++++++
src/base/SConscript | 2 +-
src/cpu/SConscript | 4 +-
src/cpu/base.hh | 9 ++++-
src/cpu/intr_control_noisa.cc | 54 ++++++++++++++++++++++++++++++++
src/dev/SConscript | 2 +-
src/dev/sinic.cc | 2 +
src/kern/SConscript | 2 +-
src/mem/SConscript | 20 ++++++------
src/mem/cache/SConscript | 3 -
src/mem/cache/base.cc | 2 -
src/mem/cache/prefetch/SConscript | 2 -
src/mem/cache/tags/SConscript | 3 -
src/mem/cache/tags/base.cc | 1 +
src/mem/fs_translating_port_proxy.cc | 1 +
src/mem/fs_translating_port_proxy.hh | 3 +-
src/mem/port_proxy.hh | 6 +-
src/mem/ruby/SConscript | 2 +-
src/python/swig/pyobject.cc | 8 ++++-
src/sim/SConscript | 12 +++----
src/sim/arguments.hh | 1 -
src/sim/stat_control.cc | 6 ---
src/sim/system.cc | 3 +-
src/sim/system.hh | 4 ++
src/unittest/SConscript | 3 -
util/regress | 1 +
39 files changed, 575 insertions(+), 62 deletions(-)
diffs (truncated from 1055 to 300 lines):
diff -r 603e2ed487f3 -r 87d6b41749e9 build_opts/NOISA
--- a/build_opts/NOISA Wed Sep 04 13:22:56 2013 -0400
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,2 +0,0 @@
-TARGET_ISA = 'no'
-CPU_MODELS = 'no'
diff -r 603e2ed487f3 -r 87d6b41749e9 build_opts/NULL
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/build_opts/NULL Wed Sep 04 13:22:57 2013 -0400
@@ -0,0 +1,2 @@
+TARGET_ISA = 'null'
+CPU_MODELS = ''
diff -r 603e2ed487f3 -r 87d6b41749e9 src/arch/generic/SConscript
--- a/src/arch/generic/SConscript Wed Sep 04 13:22:56 2013 -0400
+++ b/src/arch/generic/SConscript Wed Sep 04 13:22:57 2013 -0400
@@ -28,4 +28,7 @@
Import('*')
+if env['TARGET_ISA'] == 'null':
+ Return()
+
Source('decode_cache.cc')
diff -r 603e2ed487f3 -r 87d6b41749e9 src/arch/noisa/SConsopts
--- a/src/arch/noisa/SConsopts Wed Sep 04 13:22:56 2013 -0400
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,4 +0,0 @@
-
-Import('*')
-
-all_isa_list.append('no')
diff -r 603e2ed487f3 -r 87d6b41749e9 src/arch/noisa/cpu_dummy.hh
--- a/src/arch/noisa/cpu_dummy.hh Wed Sep 04 13:22:56 2013 -0400
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,7 +0,0 @@
-
-class BaseCPU
-{
- public:
- static int numSimulatedInsts() { return 0; }
- static int numSimulatedOps() { return 0; }
-};
diff -r 603e2ed487f3 -r 87d6b41749e9 src/arch/null/SConscript
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/src/arch/null/SConscript Wed Sep 04 13:22:57 2013 -0400
@@ -0,0 +1,43 @@
+# -*- mode:python -*-
+
+# Copyright (c) 2013 ARM Limited
+# All rights reserved
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder. You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Andreas Hansson
+
+Import('*')
+
+if env['TARGET_ISA'] == 'null':
+ Source('cpu_dummy.cc')
diff -r 603e2ed487f3 -r 87d6b41749e9 src/arch/null/SConsopts
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/src/arch/null/SConsopts Wed Sep 04 13:22:57 2013 -0400
@@ -0,0 +1,42 @@
+# -*- mode:python -*-
+
+# Copyright (c) 2013 ARM Limited
+# All rights reserved
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder. You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Andreas Hansson
+
+Import('*')
+
+all_isa_list.append('null')
diff -r 603e2ed487f3 -r 87d6b41749e9 src/arch/null/cpu_dummy.cc
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/src/arch/null/cpu_dummy.cc Wed Sep 04 13:22:57 2013 -0400
@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2013 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Andreas Hansson
+ */
+
+/**
+ * Provide the actual storage for maxThreadsPerCPU which is declared
+ * extern and normally provided by src/cpu/base.cc
+ */
+int maxThreadsPerCPU = 1;
diff -r 603e2ed487f3 -r 87d6b41749e9 src/arch/null/cpu_dummy.hh
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/src/arch/null/cpu_dummy.hh Wed Sep 04 13:22:57 2013 -0400
@@ -0,0 +1,52 @@
+/*
+ * Copyright (c) 2013 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Andreas Hansson
+ */
+
+#ifndef __ARCH_NULL_CPU_DUMMY_HH__
+#define __ARCH_NULL_CPU_DUMMY_HH__
+
+#include "sim/core.hh"
+
+class BaseCPU
+{
+ public:
+ static int numSimulatedInsts() { return 0; }
+ static int numSimulatedOps() { return 0; }
+};
+
+#endif // __ARCH_NULL_CPU_DUMMY_HH__
diff -r 603e2ed487f3 -r 87d6b41749e9 src/arch/null/isa_traits.hh
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/src/arch/null/isa_traits.hh Wed Sep 04 13:22:57 2013 -0400
@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2013 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Andreas Hansson
+ */
+
+#ifndef __ARCH_NULL_ISA_TRAITS_HH__
+#define __ARCH_NULL_ISA_TRAITS_HH__
+
+#include "base/types.hh"
+
+namespace LittleEndianGuest {}
+
+namespace NullISA
+{
+ using namespace LittleEndianGuest;
+
+ const Addr PageShift = 12;
+ const Addr PageBytes = ULL(1) << PageShift;
+
+ const int LogVMPageSize = 12; // 4K bytes
+ const int VMPageSize = (1 << LogVMPageSize);
+
+}
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