changeset 61a0b02aa800 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=61a0b02aa800
description:
cpu: Remove all notion that we know when the cpu is misspeculating.
We have no way of knowing if a CPU model is on the wrong path with
our execute-in-execute CPU models. Don't pretend that we do.
diffstat:
src/arch/alpha/ev5.cc | 12 +++---------
src/arch/alpha/faults.cc | 11 ++++-------
src/cpu/SConscript | 3 +--
src/cpu/checker/thread_context.hh | 3 ---
src/cpu/exetrace.cc | 3 ---
src/cpu/exetrace.hh | 11 +++--------
src/cpu/inorder/inorder_trace.hh | 4 ++--
src/cpu/inorder/thread_context.hh | 8 --------
src/cpu/inteltrace.hh | 11 +++--------
src/cpu/nativetrace.hh | 10 +++-------
src/cpu/o3/thread_context.hh | 8 --------
src/cpu/simple/base.hh | 1 -
src/cpu/simple_thread.hh | 9 ---------
src/cpu/thread_context.hh | 6 ------
src/sim/faults.cc | 1 -
src/sim/insttracer.hh | 6 ++----
16 files changed, 21 insertions(+), 86 deletions(-)
diffs (truncated from 362 to 300 lines):
diff -r fae54a666162 -r 61a0b02aa800 src/arch/alpha/ev5.cc
--- a/src/arch/alpha/ev5.cc Sun Jan 25 07:22:17 2015 -0500
+++ b/src/arch/alpha/ev5.cc Sun Jan 25 07:22:26 2015 -0500
@@ -161,8 +161,7 @@
case IPR_DTB_PTE:
{
- TlbEntry &entry
- = tc->getDTBPtr()->index(!tc->misspeculating());
+ TlbEntry &entry = tc->getDTBPtr()->index(1);
retval |= ((uint64_t)entry.ppn & ULL(0x7ffffff)) << 32;
retval |= ((uint64_t)entry.xre & ULL(0xf)) << 8;
@@ -202,9 +201,6 @@
void
ISA::setIpr(int idx, uint64_t val, ThreadContext *tc)
{
- if (tc->misspeculating())
- return;
-
switch (idx) {
case IPR_PALtemp0:
case IPR_PALtemp1:
@@ -484,10 +480,8 @@
CPA::cpa()->swAutoBegin(tc, pc.npc());
- if (!misspeculating()) {
- if (kernelStats)
- kernelStats->hwrei();
- }
+ if (kernelStats)
+ kernelStats->hwrei();
// FIXME: XXX check for interrupts? XXX
return NoFault;
diff -r fae54a666162 -r 61a0b02aa800 src/arch/alpha/faults.cc
--- a/src/arch/alpha/faults.cc Sun Jan 25 07:22:17 2015 -0500
+++ b/src/arch/alpha/faults.cc Sun Jan 25 07:22:26 2015 -0500
@@ -147,8 +147,7 @@
// on VPTE loads (instead of locking the registers until IPR_VA is
// read, like the EV5). The EV6 approach is cleaner and seems to
// work with EV5 PAL code, but not the other way around.
- if (!tc->misspeculating() &&
- reqFlags.noneSet(Request::VPTE | Request::PREFETCH)) {
+ if (reqFlags.noneSet(Request::VPTE | Request::PREFETCH)) {
// set VA register with faulting address
tc->setMiscRegNoEffect(IPR_VA, vaddr);
@@ -172,11 +171,9 @@
ItbFault::invoke(ThreadContext *tc, const StaticInstPtr &inst)
{
if (FullSystem) {
- if (!tc->misspeculating()) {
- tc->setMiscRegNoEffect(IPR_ITB_TAG, pc);
- tc->setMiscRegNoEffect(IPR_IFAULT_VA_FORM,
- tc->readMiscRegNoEffect(IPR_IVPTBR) | (VAddr(pc).vpn() << 3));
- }
+ tc->setMiscRegNoEffect(IPR_ITB_TAG, pc);
+ tc->setMiscRegNoEffect(IPR_IFAULT_VA_FORM,
+ tc->readMiscRegNoEffect(IPR_IVPTBR) | (VAddr(pc).vpn() << 3));
}
AlphaFault::invoke(tc);
diff -r fae54a666162 -r 61a0b02aa800 src/cpu/SConscript
--- a/src/cpu/SConscript Sun Jan 25 07:22:17 2015 -0500
+++ b/src/cpu/SConscript Sun Jan 25 07:22:26 2015 -0500
@@ -81,7 +81,6 @@
DebugFlag('ExecOpClass', 'Format: Include operand class')
DebugFlag('ExecRegDelta')
DebugFlag('ExecResult', 'Format: Include results from execution')
-DebugFlag('ExecSpeculative', 'Format: Include a miss-/speculation flag (-/+)')
DebugFlag('ExecSymbol', 'Format: Try to include symbol names')
DebugFlag('ExecThread', 'Format: Include thread ID in trace')
DebugFlag('ExecTicks', 'Format: Include tick count')
@@ -100,7 +99,7 @@
CompoundFlag('ExecAll', [ 'ExecEnable', 'ExecCPSeq', 'ExecEffAddr',
'ExecFaulting', 'ExecFetchSeq', 'ExecOpClass', 'ExecRegDelta',
- 'ExecResult', 'ExecSpeculative', 'ExecSymbol', 'ExecThread',
+ 'ExecResult', 'ExecSymbol', 'ExecThread',
'ExecTicks', 'ExecMicro', 'ExecMacro', 'ExecUser', 'ExecKernel',
'ExecAsid', 'ExecFlags' ])
CompoundFlag('Exec', [ 'ExecEnable', 'ExecTicks', 'ExecOpClass', 'ExecThread',
diff -r fae54a666162 -r 61a0b02aa800 src/cpu/checker/thread_context.hh
--- a/src/cpu/checker/thread_context.hh Sun Jan 25 07:22:17 2015 -0500
+++ b/src/cpu/checker/thread_context.hh Sun Jan 25 07:22:26 2015 -0500
@@ -310,9 +310,6 @@
actualTC->setStCondFailures(sc_failures);
}
- // @todo: Fix this!
- bool misspeculating() { return actualTC->misspeculating(); }
-
Counter readFuncExeInst() { return actualTC->readFuncExeInst(); }
uint64_t readIntRegFlat(int idx)
diff -r fae54a666162 -r 61a0b02aa800 src/cpu/exetrace.cc
--- a/src/cpu/exetrace.cc Sun Jan 25 07:22:17 2015 -0500
+++ b/src/cpu/exetrace.cc Sun Jan 25 07:22:26 2015 -0500
@@ -71,9 +71,6 @@
outs << thread->getCpuPtr()->name() << " ";
- if (Debug::ExecSpeculative)
- outs << (misspeculating ? "-" : "+") << " ";
-
if (Debug::ExecAsid)
outs << "A" << dec << TheISA::getExecutingAsid(thread) << " ";
diff -r fae54a666162 -r 61a0b02aa800 src/cpu/exetrace.hh
--- a/src/cpu/exetrace.hh Sun Jan 25 07:22:17 2015 -0500
+++ b/src/cpu/exetrace.hh Sun Jan 25 07:22:26 2015 -0500
@@ -37,7 +37,6 @@
#include "cpu/static_inst.hh"
#include "cpu/thread_context.hh"
#include "debug/ExecEnable.hh"
-#include "debug/ExecSpeculative.hh"
#include "params/ExeTracer.hh"
#include "sim/insttracer.hh"
@@ -50,9 +49,8 @@
public:
ExeTracerRecord(Tick _when, ThreadContext *_thread,
const StaticInstPtr _staticInst, TheISA::PCState _pc,
- bool spec, const StaticInstPtr _macroStaticInst = NULL)
- : InstRecord(_when, _thread, _staticInst, _pc, spec,
- _macroStaticInst)
+ const StaticInstPtr _macroStaticInst = NULL)
+ : InstRecord(_when, _thread, _staticInst, _pc, _macroStaticInst)
{
}
@@ -80,11 +78,8 @@
if (!Trace::enabled)
return NULL;
- if (!Debug::ExecSpeculative && tc->misspeculating())
- return NULL;
-
return new ExeTracerRecord(when, tc,
- staticInst, pc, tc->misspeculating(), macroStaticInst);
+ staticInst, pc, macroStaticInst);
}
};
diff -r fae54a666162 -r 61a0b02aa800 src/cpu/inorder/inorder_trace.hh
--- a/src/cpu/inorder/inorder_trace.hh Sun Jan 25 07:22:17 2015 -0500
+++ b/src/cpu/inorder/inorder_trace.hh Sun Jan 25 07:22:26 2015 -0500
@@ -47,8 +47,8 @@
{
public:
InOrderTraceRecord(unsigned num_stages, bool _stage_tracing,
- ThreadContext *_thread, TheISA::PCState _pc, bool spec = false)
- : ExeTracerRecord(0, _thread, NULL, _pc, spec)
+ ThreadContext *_thread, TheISA::PCState _pc)
+ : ExeTracerRecord(0, _thread, NULL, _pc)
{
stageTrace = _stage_tracing;
stageCycle.resize(num_stages);
diff -r fae54a666162 -r 61a0b02aa800 src/cpu/inorder/thread_context.hh
--- a/src/cpu/inorder/thread_context.hh Sun Jan 25 07:22:17 2015 -0500
+++ b/src/cpu/inorder/thread_context.hh Sun Jan 25 07:22:26 2015 -0500
@@ -290,14 +290,6 @@
void setStCondFailures(unsigned sc_failures)
{ thread->storeCondFailures = sc_failures; }
- // Only really makes sense for old CPU model. Lots of code
- // outside the CPU still checks this function, so it will
- // always return false to keep everything working.
- /** Checks if the thread is misspeculating. Because it is
- * very difficult to determine if the thread is
- * misspeculating, this is set as false. */
- bool misspeculating() { return false; }
-
/** Executes a syscall in SE mode. */
void syscall(int64_t callnum)
{ return cpu->syscall(callnum, thread->threadId()); }
diff -r fae54a666162 -r 61a0b02aa800 src/cpu/inteltrace.hh
--- a/src/cpu/inteltrace.hh Sun Jan 25 07:22:17 2015 -0500
+++ b/src/cpu/inteltrace.hh Sun Jan 25 07:22:26 2015 -0500
@@ -37,7 +37,6 @@
#include "cpu/static_inst.hh"
#include "cpu/thread_context.hh"
#include "debug/ExecEnable.hh"
-#include "debug/ExecSpeculative.hh"
#include "params/IntelTrace.hh"
#include "sim/insttracer.hh"
@@ -48,8 +47,8 @@
public:
IntelTraceRecord(Tick _when, ThreadContext *_thread,
const StaticInstPtr _staticInst, TheISA::PCState _pc,
- bool spec, const StaticInstPtr _macroStaticInst = NULL)
- : InstRecord(_when, _thread, _staticInst, _pc, spec,
+ const StaticInstPtr _macroStaticInst = NULL)
+ : InstRecord(_when, _thread, _staticInst, _pc,
_macroStaticInst)
{
}
@@ -75,11 +74,7 @@
if (!Trace::enabled)
return NULL;
- if (!Debug::ExecSpeculative && tc->misspeculating())
- return NULL;
-
- return new IntelTraceRecord(when, tc,
- staticInst, pc, tc->misspeculating(), macroStaticInst);
+ return new IntelTraceRecord(when, tc, staticInst, pc, macroStaticInst);
}
};
diff -r fae54a666162 -r 61a0b02aa800 src/cpu/nativetrace.hh
--- a/src/cpu/nativetrace.hh Sun Jan 25 07:22:17 2015 -0500
+++ b/src/cpu/nativetrace.hh Sun Jan 25 07:22:26 2015 -0500
@@ -56,9 +56,8 @@
NativeTraceRecord(NativeTrace * _parent,
Tick _when, ThreadContext *_thread,
const StaticInstPtr _staticInst, TheISA::PCState _pc,
- bool spec, const StaticInstPtr _macroStaticInst = NULL)
- : ExeTracerRecord(_when, _thread, _staticInst, _pc, spec,
- _macroStaticInst),
+ const StaticInstPtr _macroStaticInst = NULL)
+ : ExeTracerRecord(_when, _thread, _staticInst, _pc, _macroStaticInst),
parent(_parent)
{
}
@@ -83,11 +82,8 @@
const StaticInstPtr staticInst, TheISA::PCState pc,
const StaticInstPtr macroStaticInst = NULL)
{
- if (tc->misspeculating())
- return NULL;
-
return new NativeTraceRecord(this, when, tc,
- staticInst, pc, tc->misspeculating(), macroStaticInst);
+ staticInst, pc, macroStaticInst);
}
template<class T>
diff -r fae54a666162 -r 61a0b02aa800 src/cpu/o3/thread_context.hh
--- a/src/cpu/o3/thread_context.hh Sun Jan 25 07:22:17 2015 -0500
+++ b/src/cpu/o3/thread_context.hh Sun Jan 25 07:22:26 2015 -0500
@@ -257,14 +257,6 @@
virtual void setStCondFailures(unsigned sc_failures)
{ thread->storeCondFailures = sc_failures; }
- // Only really makes sense for old CPU model. Lots of code
- // outside the CPU still checks this function, so it will
- // always return false to keep everything working.
- /** Checks if the thread is misspeculating. Because it is
- * very difficult to determine if the thread is
- * misspeculating, this is set as false. */
- virtual bool misspeculating() { return false; }
-
/** Executes a syscall in SE mode. */
virtual void syscall(int64_t callnum)
{ return cpu->syscall(callnum, thread->threadId()); }
diff -r fae54a666162 -r 61a0b02aa800 src/cpu/simple/base.hh
--- a/src/cpu/simple/base.hh Sun Jan 25 07:22:17 2015 -0500
+++ b/src/cpu/simple/base.hh Sun Jan 25 07:22:26 2015 -0500
@@ -449,7 +449,6 @@
thread->syscall(callnum);
}
- bool misspeculating() { return thread->misspeculating(); }
ThreadContext *tcBase() { return tc; }
private:
diff -r fae54a666162 -r 61a0b02aa800 src/cpu/simple_thread.hh
--- a/src/cpu/simple_thread.hh Sun Jan 25 07:22:17 2015 -0500
+++ b/src/cpu/simple_thread.hh Sun Jan 25 07:22:26 2015 -0500
@@ -220,8 +220,6 @@
/// Set the status to Halted.
void halt();
- virtual bool misspeculating();
-
void copyArchRegs(ThreadContext *tc);
void clearArchRegs()
@@ -455,11 +453,4 @@
};
-// for non-speculative execution context, spec_mode is always false
-inline bool
-SimpleThread::misspeculating()
-{
- return false;
-}
-
#endif // __CPU_CPU_EXEC_CONTEXT_HH__
diff -r fae54a666162 -r 61a0b02aa800 src/cpu/thread_context.hh
--- a/src/cpu/thread_context.hh Sun Jan 25 07:22:17 2015 -0500
+++ b/src/cpu/thread_context.hh Sun Jan 25 07:22:26 2015 -0500
@@ -255,9 +255,6 @@
virtual void setStCondFailures(unsigned sc_failures) = 0;
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