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Review request for Default. Repository: gem5 Description ------- Changeset 10735:c8c9b6d902cb --------------------------- cpu: o3: record cpi stacks This patch labels each empty slot of the commit width every cycle using four different types of delays: misprediction, fetch, memory and execution. For memory delays, we check if a memory reference instruction is at the head of the rob. Otherwise, we label the slot as execution delayed. If the rob is empty, we assume the reason for the vacancy to be delay in fetching the instuction. Lastly, if the cpu is squashing instructions, then we assume that slots are going vacant because of misprediction. Diffs ----- src/cpu/o3/commit.hh 8a20e2a1562d src/cpu/o3/commit_impl.hh 8a20e2a1562d Diff: http://reviews.gem5.org/r/2680/diff/ Testing ------- Thanks, Nilay Vaish _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
