> On July 6, 2015, 12:42 p.m., Giacomo Gabrielli wrote: > > These are my current thoughts about this patch: > > > > 1. My impression is that there is still not enough architectural support to > > understand if the new vector register type as it stands can address all the > > different corner cases efficiently; I'd leave to the wider gem5 community > > decide where we want to draw that line... > > > > 2. Legacy SSE requires merging of upper lanes, while AVX does zeroing; also > > ARMv8 AArch64 scalar FP and NEON instructions perform zeroing. Assuming that > > destination vectors are always read is going to introduce unneded > > serialization for those ISA extensions if they are going to be ported to > > the new scheme, so I'd suggest to avoid to implicitly read on write. > > Also for cases where merging is required, maybe something smarter should be > > done to avoid unneded serialization; without optimizations, any sequence of > > x86 FP scalar instructions could be significantly slow compared to real hw > > implementations.
Could you please detail a bit the merging issue for legacy SSE? - Alexandru ----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2828/#review6715 ----------------------------------------------------------- On July 1, 2015, 10:13 p.m., Nilay Vaish wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/2828/ > ----------------------------------------------------------- > > (Updated July 1, 2015, 10:13 p.m.) > > > Review request for Default. > > > Repository: gem5 > > > Description > ------- > > Changeset 10880:f9a35df0dce5 > --------------------------- > cpu: implements vector registers > > This patch aims at adding vector registers type. The type is defined > as a std::array of some fixed number of uint64_ts. The isa_parser.py > has been modified to parse vector register operands and generate the > required code. Different cpus have vector register files now. > > > Diffs > ----- > > src/cpu/StaticInstFlags.py 73d4798871a5 > src/cpu/base_dyn_inst.hh 73d4798871a5 > src/cpu/checker/cpu.hh 73d4798871a5 > src/cpu/checker/cpu_impl.hh 73d4798871a5 > src/cpu/checker/thread_context.hh 73d4798871a5 > src/cpu/exec_context.hh 73d4798871a5 > src/cpu/minor/dyn_inst.cc 73d4798871a5 > src/cpu/minor/exec_context.hh 73d4798871a5 > src/cpu/minor/scoreboard.hh 73d4798871a5 > src/cpu/minor/scoreboard.cc 73d4798871a5 > src/cpu/o3/O3CPU.py 73d4798871a5 > src/cpu/o3/cpu.hh 73d4798871a5 > src/cpu/o3/cpu.cc 73d4798871a5 > src/cpu/o3/dyn_inst.hh 73d4798871a5 > src/cpu/o3/free_list.hh 73d4798871a5 > src/cpu/o3/inst_queue_impl.hh 73d4798871a5 > src/cpu/o3/regfile.hh 73d4798871a5 > src/cpu/o3/regfile.cc 73d4798871a5 > src/cpu/o3/rename_impl.hh 73d4798871a5 > src/cpu/o3/rename_map.hh 73d4798871a5 > src/cpu/o3/rename_map.cc 73d4798871a5 > src/cpu/o3/thread_context.hh 73d4798871a5 > src/cpu/o3/thread_context_impl.hh 73d4798871a5 > src/cpu/reg_class.hh 73d4798871a5 > src/cpu/simple/base.hh 73d4798871a5 > src/cpu/simple_thread.hh 73d4798871a5 > src/cpu/static_inst.hh 73d4798871a5 > src/cpu/thread_context.hh 73d4798871a5 > src/cpu/thread_context.cc 73d4798871a5 > src/sim/insttracer.hh 73d4798871a5 > src/arch/SConscript 73d4798871a5 > src/arch/alpha/isa.hh 73d4798871a5 > src/arch/alpha/registers.hh 73d4798871a5 > src/arch/alpha/utility.cc 73d4798871a5 > src/arch/arm/insts/static_inst.cc 73d4798871a5 > src/arch/arm/isa.hh 73d4798871a5 > src/arch/arm/registers.hh 73d4798871a5 > src/arch/arm/utility.cc 73d4798871a5 > src/arch/isa_parser.py 73d4798871a5 > src/arch/mips/isa.hh 73d4798871a5 > src/arch/mips/registers.hh 73d4798871a5 > src/arch/mips/utility.cc 73d4798871a5 > src/arch/null/registers.hh 73d4798871a5 > src/arch/power/isa.hh 73d4798871a5 > src/arch/power/registers.hh 73d4798871a5 > src/arch/power/utility.cc 73d4798871a5 > src/arch/sparc/isa.hh 73d4798871a5 > src/arch/sparc/registers.hh 73d4798871a5 > src/arch/sparc/utility.cc 73d4798871a5 > src/arch/x86/insts/static_inst.cc 73d4798871a5 > src/arch/x86/isa.hh 73d4798871a5 > src/arch/x86/registers.hh 73d4798871a5 > src/arch/x86/utility.cc 73d4798871a5 > > Diff: http://reviews.gem5.org/r/2828/diff/ > > > Testing > ------- > > > Thanks, > > Nilay Vaish > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
