> On June 29, 2015, 11:05 a.m., Andreas Sandberg wrote: > > src/sim/insttracer.hh, lines 120-128 > > <http://reviews.gem5.org/r/2828/diff/7/?file=47161#file47161line120> > > > > Does this break length assumptions?
I am replacing 16 with sizeof(VectorReg). On June 29, 2015, 11:05 a.m., Nilay Vaish wrote: > > I think you are missing serialization support for vector registers. See > > serialize() and unserialize() in thread_context.cc. > > Andreas Sandberg wrote: > Note: This is in addition to the issues Giacomo highlighted above. Have > you had a chance to look into how overlapping registers are going to be > handled? Will this just work? > > Another thing I just remembered -- I'm pretty sure I read somewhere that > you're flagging all vector accesses and reads since you aren't necessarily > overwriting every single element in the vector. Does this really make sense? I have added the code for serialize and unserialize. As far as xmm, ymm and zmm registers are concerned, we will represent them using the same register. In the microcode, we will specify the length of the register to be read / written, depending on the type of register in use. The patch for moving all the sse code using xmm registers has already been posted. I think you are referring to the following comment in isa_parser.py: ## Vector registers are always treated as source registers since ## not the whole of them might be written, in which case we need ## to retain the earlier value. If we treat a given vector register as only a destination register, then its initial value would not be read. So, we do need some such thing in place. We might want to add a check that this does not need to happen when we are going to write the whole register. - Nilay ----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2828/#review6642 ----------------------------------------------------------- On June 27, 2015, 12:35 a.m., Nilay Vaish wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/2828/ > ----------------------------------------------------------- > > (Updated June 27, 2015, 12:35 a.m.) > > > Review request for Default. > > > Repository: gem5 > > > Description > ------- > > Changeset 10881:99af6364a97a > --------------------------- > cpu: implements vector registers > > This patch aims at adding vector registers type. The type is defined > as a std::array of some fixed number of uint64_ts. The isa_parser.py > has been modified to parse vector register operands and generate the > required code. Different cpus have vector register files now. > > > Diffs > ----- > > src/cpu/checker/cpu.hh 73d4798871a5 > src/cpu/checker/cpu_impl.hh 73d4798871a5 > src/cpu/checker/thread_context.hh 73d4798871a5 > src/cpu/exec_context.hh 73d4798871a5 > src/cpu/minor/dyn_inst.cc 73d4798871a5 > src/cpu/minor/exec_context.hh 73d4798871a5 > src/cpu/minor/scoreboard.cc 73d4798871a5 > src/cpu/o3/O3CPU.py 73d4798871a5 > src/cpu/o3/cpu.hh 73d4798871a5 > src/cpu/o3/cpu.cc 73d4798871a5 > src/cpu/o3/dyn_inst.hh 73d4798871a5 > src/cpu/o3/free_list.hh 73d4798871a5 > src/cpu/o3/inst_queue_impl.hh 73d4798871a5 > src/cpu/o3/regfile.hh 73d4798871a5 > src/cpu/o3/regfile.cc 73d4798871a5 > src/cpu/o3/rename_impl.hh 73d4798871a5 > src/cpu/o3/rename_map.hh 73d4798871a5 > src/cpu/o3/rename_map.cc 73d4798871a5 > src/cpu/o3/thread_context.hh 73d4798871a5 > src/cpu/o3/thread_context_impl.hh 73d4798871a5 > src/cpu/reg_class.hh 73d4798871a5 > src/cpu/simple/base.hh 73d4798871a5 > src/cpu/simple_thread.hh 73d4798871a5 > src/cpu/static_inst.hh 73d4798871a5 > src/cpu/thread_context.hh 73d4798871a5 > src/sim/insttracer.hh 73d4798871a5 > src/arch/x86/registers.hh 73d4798871a5 > src/cpu/StaticInstFlags.py 73d4798871a5 > src/cpu/base_dyn_inst.hh 73d4798871a5 > src/arch/SConscript 73d4798871a5 > src/arch/alpha/isa.hh 73d4798871a5 > src/arch/alpha/registers.hh 73d4798871a5 > src/arch/arm/insts/static_inst.cc 73d4798871a5 > src/arch/arm/isa.hh 73d4798871a5 > src/arch/arm/registers.hh 73d4798871a5 > src/arch/isa_parser.py 73d4798871a5 > src/arch/mips/isa.hh 73d4798871a5 > src/arch/mips/registers.hh 73d4798871a5 > src/arch/null/registers.hh 73d4798871a5 > src/arch/power/isa.hh 73d4798871a5 > src/arch/power/registers.hh 73d4798871a5 > src/arch/sparc/isa.hh 73d4798871a5 > src/arch/sparc/registers.hh 73d4798871a5 > src/arch/x86/insts/static_inst.cc 73d4798871a5 > src/arch/x86/isa.hh 73d4798871a5 > > Diff: http://reviews.gem5.org/r/2828/diff/ > > > Testing > ------- > > > Thanks, > > Nilay Vaish > > _______________________________________________ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
