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Review request for Default. Repository: gem5 Description ------- Changeset 11428:52997ce5a9a3 --------------------------- ruby: DataBlock method changes w/ manual subsequent initializations The data block initialization depended on the statically declared block size for its internal bitmask. We change the default behavior to initialize an empty bitmask in cases where the block size cannot be passed via a parameter list; subsequently we immediately initialize the data block with the size for objects that need the data block. Diffs ----- src/mem/protocol/MOESI_CMP_token-dir.sm cfad34a15729e1d5e096245f5a80ded6e2c379ca src/mem/protocol/MOESI_hammer-cache.sm cfad34a15729e1d5e096245f5a80ded6e2c379ca src/mem/protocol/MOESI_hammer-dir.sm cfad34a15729e1d5e096245f5a80ded6e2c379ca src/mem/protocol/Network_test-cache.sm cfad34a15729e1d5e096245f5a80ded6e2c379ca src/mem/protocol/RubySlicc_Exports.sm cfad34a15729e1d5e096245f5a80ded6e2c379ca src/mem/ruby/common/DataBlock.hh cfad34a15729e1d5e096245f5a80ded6e2c379ca src/mem/ruby/common/DataBlock.cc cfad34a15729e1d5e096245f5a80ded6e2c379ca src/mem/ruby/slicc_interface/AbstractController.cc cfad34a15729e1d5e096245f5a80ded6e2c379ca src/mem/ruby/system/GPUCoalescer.cc cfad34a15729e1d5e096245f5a80ded6e2c379ca src/mem/protocol/MOESI_CMP_directory-L1cache.sm cfad34a15729e1d5e096245f5a80ded6e2c379ca src/mem/protocol/MOESI_CMP_directory-L2cache.sm cfad34a15729e1d5e096245f5a80ded6e2c379ca src/mem/protocol/MOESI_CMP_directory-dir.sm cfad34a15729e1d5e096245f5a80ded6e2c379ca src/mem/protocol/MOESI_CMP_directory-dma.sm cfad34a15729e1d5e096245f5a80ded6e2c379ca src/mem/protocol/MOESI_CMP_token-L1cache.sm cfad34a15729e1d5e096245f5a80ded6e2c379ca src/mem/protocol/MOESI_CMP_token-L2cache.sm cfad34a15729e1d5e096245f5a80ded6e2c379ca src/mem/protocol/MESI_Two_Level-dir.sm cfad34a15729e1d5e096245f5a80ded6e2c379ca src/mem/protocol/MI_example-cache.sm cfad34a15729e1d5e096245f5a80ded6e2c379ca src/mem/protocol/MI_example-dir.sm cfad34a15729e1d5e096245f5a80ded6e2c379ca src/mem/protocol/MOESI_AMD_Base-CorePair.sm cfad34a15729e1d5e096245f5a80ded6e2c379ca src/mem/protocol/MOESI_AMD_Base-L3cache.sm cfad34a15729e1d5e096245f5a80ded6e2c379ca src/mem/protocol/MOESI_AMD_Base-Region-CorePair.sm cfad34a15729e1d5e096245f5a80ded6e2c379ca src/mem/protocol/MOESI_AMD_Base-Region-dir.sm cfad34a15729e1d5e096245f5a80ded6e2c379ca src/mem/protocol/MOESI_AMD_Base-RegionBuffer.sm cfad34a15729e1d5e096245f5a80ded6e2c379ca src/mem/protocol/MOESI_AMD_Base-RegionDir.sm cfad34a15729e1d5e096245f5a80ded6e2c379ca src/mem/protocol/MOESI_AMD_Base-dir.sm cfad34a15729e1d5e096245f5a80ded6e2c379ca src/mem/protocol/MOESI_AMD_Base-probeFilter.sm cfad34a15729e1d5e096245f5a80ded6e2c379ca src/mem/protocol/GPU_VIPER-TCP.sm cfad34a15729e1d5e096245f5a80ded6e2c379ca src/mem/protocol/GPU_VIPER_Region-TCC.sm cfad34a15729e1d5e096245f5a80ded6e2c379ca src/mem/protocol/MESI_Three_Level-L0cache.sm cfad34a15729e1d5e096245f5a80ded6e2c379ca src/mem/protocol/MESI_Three_Level-L1cache.sm cfad34a15729e1d5e096245f5a80ded6e2c379ca src/mem/protocol/MESI_Two_Level-L1cache.sm cfad34a15729e1d5e096245f5a80ded6e2c379ca src/mem/protocol/MESI_Two_Level-L2cache.sm cfad34a15729e1d5e096245f5a80ded6e2c379ca src/mem/protocol/GPU_RfO-SQC.sm cfad34a15729e1d5e096245f5a80ded6e2c379ca src/mem/protocol/GPU_RfO-TCC.sm cfad34a15729e1d5e096245f5a80ded6e2c379ca src/mem/protocol/GPU_RfO-TCCdir.sm cfad34a15729e1d5e096245f5a80ded6e2c379ca src/mem/protocol/GPU_RfO-TCP.sm cfad34a15729e1d5e096245f5a80ded6e2c379ca src/mem/protocol/GPU_VIPER-SQC.sm cfad34a15729e1d5e096245f5a80ded6e2c379ca src/mem/protocol/GPU_VIPER-TCC.sm cfad34a15729e1d5e096245f5a80ded6e2c379ca Diff: http://reviews.gem5.org/r/3426/diff/ Testing ------- Thanks, Brandon Potter _______________________________________________ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
