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Can you please update it? It neither applies cleanly nor does it compile afterwards. - Bjoern A. Zeeb On Jan. 19, 2016, 3:46 a.m., Steve Reinhardt wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/2691/ > ----------------------------------------------------------- > > (Updated Jan. 19, 2016, 3:46 a.m.) > > > Review request for Default. > > > Repository: gem5 > > > Description > ------- > > Changeset 10745:9b84d1b570e3 > --------------------------- > mem: implement x86 locked accesses in timing-mode classic cache > > Add LockedRMW(Read|Write)(Req|Resp) commands. In timing mode, > use a combination of clearing permission bits and leaving > an MSHR in place to prevent accesses & snoops from touching > a locked block between the read and write parts of an locked > RMW sequence. > > > Diffs > ----- > > src/mem/packet.cc d06e5a6b4b7f05a642c3e2bee12cfeb130dede16 > src/mem/cache/cache.cc d06e5a6b4b7f05a642c3e2bee12cfeb130dede16 > src/mem/cache/mshr.hh d06e5a6b4b7f05a642c3e2bee12cfeb130dede16 > src/mem/packet.hh d06e5a6b4b7f05a642c3e2bee12cfeb130dede16 > > Diff: http://reviews.gem5.org/r/2691/diff/ > > > Testing > ------- > > > Thanks, > > Steve Reinhardt > > _______________________________________________ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
