> On Jan. 5, 2017, 4:32 p.m., Tony Gutierrez wrote:
> > Is there anything holding this up from being shipped?

In my view the patch needs two things:

1) Some thought around the design. I am still hoping there is a less invasive 
way of accommodating the functionality, possibly with some changes to the 
existing functions of the cache.

2) A way to test it. This should preferably include both synthetic and real 
use-cases. The memtester and memchecker may be a good starting point for the 
synthetic part.

It would be great if someone could dig into these issues.


- Andreas


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On April 15, 2016, 5:42 a.m., Steve Reinhardt wrote:
> 
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> This is an automatically generated e-mail. To reply, visit:
> http://reviews.gem5.org/r/2691/
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> 
> (Updated April 15, 2016, 5:42 a.m.)
> 
> 
> Review request for Default.
> 
> 
> Repository: gem5
> 
> 
> Description
> -------
> 
> Changeset 11444:8a1419dbbfa6
> ---------------------------
> mem: implement x86 locked accesses in timing-mode classic cache
> 
> Add LockedRMW(Read|Write)(Req|Resp) commands.  In timing mode,
> use a combination of clearing permission bits and leaving
> an MSHR in place to prevent accesses & snoops from touching
> a locked block between the read and write parts of an locked
> RMW sequence.
> 
> 
> Diffs
> -----
> 
>   src/mem/cache/cache.cc df24b9af42c72606f1fa8e5aa0502b53e81ea176 
>   src/mem/cache/mshr.hh df24b9af42c72606f1fa8e5aa0502b53e81ea176 
>   src/mem/packet.hh df24b9af42c72606f1fa8e5aa0502b53e81ea176 
>   src/mem/packet.cc df24b9af42c72606f1fa8e5aa0502b53e81ea176 
> 
> Diff: http://reviews.gem5.org/r/2691/diff/
> 
> 
> Testing
> -------
> 
> 
> Thanks,
> 
> Steve Reinhardt
> 
>

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