> On juil. 25, 2016, 1:18 après-midi, Nikos Nikoleris wrote:
> > Ship It!
>
> Sophiane SENNI wrote:
> How can I commit the patch ? I am not sure I have the commit access ?
>
> Nikos Nikoleris wrote:
> You can't commit it youself, one of the maintainers will have to commit
> it for you.
>
> Jason Lowe-Power wrote:
> Hi Sophanie,
>
> Have you run all of the regression tests? Are there changes to the stats
> (I would expect so)? Have you checked to make sure the stat changes make
> intuitive sense? Thanks!
>
> Also, it would be nice to see Andreas H., or Steve, or someone who has
> been modifying the cache code lately to take a quick look at this patch
> before it's committed.
>
> Sophiane SENNI wrote:
> Hi Jason,
>
> I did not run any regression test. I only checked (with
> --debug-flags=Cache) if the cache access latencies were correct for:
> - hits and misses
> - parallel and sequential accesses
> Regarding the stats, I only checked if the "sim_seconds" changes were
> intuitive when modifying:
> - tag_latency and data_latency
> - cache access mode (i.e. sequential_access = True or False)
>
> Jason Lowe-Power wrote:
> Please run all of the regression tests that you can (e.g., the ones that
> don't require proprietary binaries). I know there are some other config files
> that will need to be changed (e.g., the learning_gem5 scripts), and there may
> be others.
>
> Also, I expect this will require another patch to update the stats, too.
> But you don't have to post that one on reviewboard :).
>
> Sophiane SENNI wrote:
> I ran the following command: "scons build/ARM/tests/opt/quick/se"
> The output seems to be the same as when compiling gem5 with the command
> "scons build/ARM/gem5.opt". Is it normal ?
> I expected to get outputs like the following one: "*****
> build/ARM/tests/opt/quick/se/00.hello/arm/linux/minor-timing: passed."
>
> Sophiane SENNI wrote:
> I successfully launched the regression tests. You are right. Some config
> files need to be changed. For instance, the "O3_ARM_v7a.py" file where the
> "hit_latency" has to be replaced by the two new parameters "tag_latency" and
> "data_latency". I will try to make all necessary changes according to the
> regression tests results.
Jason,
Below are the results of the regression tests I ran:
***** build/ARM/tests/opt/quick/se/00.hello/arm/linux/minor-timing: passed.
***** build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing: passed.
***** build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker: passed.
***** build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic: passed.
*****
build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic-dummychecker:
passed.
***** build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-timing: passed.
*****
build/ARM/tests/opt/quick/se/03.learning-gem5/arm/linux/learning-gem5-p1-simple:
passed.
*****
build/ARM/tests/opt/quick/se/03.learning-gem5/arm/linux/learning-gem5-p1-two-level:
FAILED!
The last test failed with the following error (Do you know how to resolve it ?):
File
"/home/senni/Partage/shared_folder_gem5/gem5/gem5_from_mercurial/gem5/tests/testing/../../configs/learning_gem5/part1/two_level.py",
line 93, in <module>
system.cpu.icache = L1ICache(opts)
NameError: name 'L1ICache' is not defined
For the fs mode regression tests, it fails with the following error:
File
"/home/senni/Partage/shared_folder_gem5/gem5/gem5_from_mercurial/gem5/configs/common/SysPaths.py",
line 69, in system
raise IOError, "Can't find a path to system files."
IOError: Can't find a path to system files.
I have this error even if the $M5_PATH variable is correctly set.
- Sophiane
-----------------------------------------------------------
This is an automatically generated e-mail. To reply, visit:
http://reviews.gem5.org/r/3502/#review8525
-----------------------------------------------------------
On juil. 28, 2016, 10:31 matin, Sophiane SENNI wrote:
>
> -----------------------------------------------------------
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.gem5.org/r/3502/
> -----------------------------------------------------------
>
> (Updated juil. 28, 2016, 10:31 matin)
>
>
> Review request for Default.
>
>
> Repository: gem5
>
>
> Description
> -------
>
> Changeset 11536:1a3a96d435ed
> ---------------------------
> mem: Split the hit_latency into tag_latency and data_latency
>
> If the cache access mode is parallel, i.e. "sequential_access" parameter
> is set to "False", tags and data are accessed in parallel. Therefore,
> the hit_latency is the maximum latency between tag_latency and
> data_latency. On the other hand, if the cache access mode is
> sequential, i.e. "sequential_access" parameter is set to "True",
> tags and data are accessed sequentially. Therefore, the hit_latency
> is the sum of tag_latency plus data_latency.
>
>
> Diffs
> -----
>
> configs/common/Caches.py 4aac82f109517217e6bfb3812689280e7a8fa842
> configs/common/O3_ARM_v7a.py 4aac82f109517217e6bfb3812689280e7a8fa842
> src/mem/cache/Cache.py 4aac82f109517217e6bfb3812689280e7a8fa842
> src/mem/cache/base.hh 4aac82f109517217e6bfb3812689280e7a8fa842
> src/mem/cache/base.cc 4aac82f109517217e6bfb3812689280e7a8fa842
> src/mem/cache/tags/Tags.py 4aac82f109517217e6bfb3812689280e7a8fa842
> src/mem/cache/tags/base.hh 4aac82f109517217e6bfb3812689280e7a8fa842
> src/mem/cache/tags/base.cc 4aac82f109517217e6bfb3812689280e7a8fa842
> src/mem/cache/tags/base_set_assoc.hh
> 4aac82f109517217e6bfb3812689280e7a8fa842
> src/mem/cache/tags/fa_lru.cc 4aac82f109517217e6bfb3812689280e7a8fa842
>
> Diff: http://reviews.gem5.org/r/3502/diff/
>
>
> Testing
> -------
>
> Tested using --Debug-flags=Cache
>
>
> Thanks,
>
> Sophiane SENNI
>
>
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