Hi all, I would like to add a new hardware component in gem5. This component will be at the same level than L1 caches. I am planning to modify the base cpu to add a new port and use it to communicate with my component.
Eventually, I would like to share my work with the gem5 community. Louisa Bessad (from my lab) had a discussion with Gabor Dozsa from ARM and told me that any modification to the base cpu must be strongly justified to the developers, and so could be very hard to merge in gem5. So, my questions are: - can I do what I want without modifying the base cpu ? - if not, what are the chances that my work will be accepted ? Thank you all. -- +-------------------------------------------------------------+ | Pierre-Yves Péneau - PhD student | first.last at lirmm.fr | | LIRMM / CNRS - SYSMIC team | + 33 4 67 41 86 33 | | Building 4 Office H2.2 | http://walafc0.org | +-------------------------------------------------------------+ _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
