Hello Everyone, Over the past few days I've been building a seventh patch to add to my original series of five (now six) that adds RISC-V to add regression tests for each instruction. In doing so I've discovered that the LLSC code I copied from MIPS may not have been sufficient for RISC-V's LR and SC instructions, the fact of which slipped through my tests during my initial implementation. Since this is a pretty big change, the read-modify-write instructions work fine (and so do LR and SC except for SC's success code result), and the fix also depends on patch 5, I'm going to leave patch 4 as it is and implement the corrections in a new patch that will come out before the regression patch.
Also, I would have preferred to say this in a comment to patch 4 on the review board, but I couldn't find a comment field. Is there one? -Alec Roelke _______________________________________________ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
