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Review request for Default. Repository: gem5 Description ------- Changeset 11694:1c3068cb5c86 --------------------------- riscv: [Patch 7/5] Corrected LRSC semantics RISC-V makes use of load-reserved and store-conditional instructions to enable creation of lock-free concurrent data manipulation as well as ACQUIRE and RELEASE semantics for memory ordering of LR, SC, and AMO instructions (the latter of which do not follow LR/SC semantics). This patch is a correction to patch 4, which added these instructions to the implementation of RISC-V. It modifies locked_mem.hh and the implementations of lr.w, sc.w, lr.d, and sc.d to apply the proper gem5 flags and return the proper values. An important difference between gem5's LLSC semantics and RISC-V's LR/SC ones, beyond the name, is that gem5 uses 0 to indicate failure and 1 to indicate success, while RISC-V is the opposite. Strictly speaking, RISC-V uses 0 to indicate success and nonzero to indicate failure where the value would indicate the error, but currently only 1 is reserved as a failure code by the ISA reference. This is the seventh patch in the series which originally consisted of five patches that added the RISC-V ISA to gem5. The original five patches added all of the instructions and added support for more detailed CPU models and the sixth patch corrected the implementations of Linux constants and structs. There will be an eighth patch that adds some regression tests for the instructions. Signed-off by: Alec Roelke Diffs ----- src/arch/riscv/isa/decoder.isa PRE-CREATION src/arch/riscv/isa/formats/mem.isa PRE-CREATION src/arch/riscv/locked_mem.hh PRE-CREATION Diff: http://reviews.gem5.org/r/3693/diff/ Testing ------- Thanks, Alec Roelke _______________________________________________ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
