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(Updated Feb. 14, 2017, 4:26 p.m.) Review request for Default. Summary (updated) ----------------- cpu: Added interface for vector reg file Repository: gem5 Description (updated) ------- Changeset 11838:6e566ea8b092 --------------------------- cpu: Added interface for vector reg file This patch adds some more functionality to the cpu model and the arch to interface with the vector register file. This change consist mainly in augmenting ThreadContexts and ExecContexts with calls to get/set full vectors, underlying microarchitectural elements or lanes. Those are meant to interface with the vector register file. All classes that implement this interface also get an appropriate implementation. This requires implementing the vector register file for the different models using the VecRegContainer class. This change set also updates the Result abstraction to contemplate the possibility of having a vector as result. The changes also affect how the remote_gdb connection works. There are some (nasty) side effects, as the need to define dummy values for architectures that do not implement vector extensions. Initialisation of numPysVecRegs in the test configurations, Nathanael Premillieu's work with an increasing number of fixes and improvements of mine. Change-Id: Iee65f4e8b03abfe1e94e6940a51b68d0977fd5bb Reviewed-by: Andreas Sandberg <andreas.sandb...@arm.com> Diffs (updated) ----- configs/common/O3_ARM_v7a.py 3c38d3e74980 src/arch/SConscript 3c38d3e74980 src/arch/alpha/isa.hh 3c38d3e74980 src/arch/alpha/registers.hh 3c38d3e74980 src/arch/arm/ArmISA.py 3c38d3e74980 src/arch/arm/insts/static_inst.hh 3c38d3e74980 src/arch/arm/insts/static_inst.cc 3c38d3e74980 src/arch/arm/isa.hh 3c38d3e74980 src/arch/arm/isa.cc 3c38d3e74980 src/arch/arm/nativetrace.cc 3c38d3e74980 src/arch/arm/registers.hh 3c38d3e74980 src/arch/arm/remote_gdb.hh 3c38d3e74980 src/arch/arm/remote_gdb.cc 3c38d3e74980 src/arch/arm/utility.cc 3c38d3e74980 src/arch/generic/ISACommon.py PRE-CREATION src/arch/generic/SConscript 3c38d3e74980 src/arch/generic/traits.hh PRE-CREATION src/arch/generic/types.hh 3c38d3e74980 src/arch/generic/vec_reg.hh PRE-CREATION src/arch/isa_parser.py 3c38d3e74980 src/arch/mips/isa.hh 3c38d3e74980 src/arch/mips/registers.hh 3c38d3e74980 src/arch/null/registers.hh 3c38d3e74980 src/arch/power/isa.hh 3c38d3e74980 src/arch/power/registers.hh 3c38d3e74980 src/arch/sparc/isa.hh 3c38d3e74980 src/arch/sparc/registers.hh 3c38d3e74980 src/arch/x86/isa.hh 3c38d3e74980 src/arch/x86/registers.hh 3c38d3e74980 src/cpu/base_dyn_inst.hh 3c38d3e74980 src/cpu/checker/cpu.hh 3c38d3e74980 src/cpu/checker/cpu_impl.hh 3c38d3e74980 src/cpu/checker/thread_context.hh 3c38d3e74980 src/cpu/exec_context.hh 3c38d3e74980 src/cpu/inst_res.hh PRE-CREATION src/cpu/minor/dyn_inst.cc 3c38d3e74980 src/cpu/minor/exec_context.hh 3c38d3e74980 src/cpu/minor/scoreboard.hh 3c38d3e74980 src/cpu/minor/scoreboard.cc 3c38d3e74980 src/cpu/o3/O3CPU.py 3c38d3e74980 src/cpu/o3/comm.hh 3c38d3e74980 src/cpu/o3/cpu.hh 3c38d3e74980 src/cpu/o3/cpu.cc 3c38d3e74980 src/cpu/o3/dyn_inst.hh 3c38d3e74980 src/cpu/o3/free_list.hh 3c38d3e74980 src/cpu/o3/inst_queue_impl.hh 3c38d3e74980 src/cpu/o3/regfile.hh 3c38d3e74980 src/cpu/o3/regfile.cc 3c38d3e74980 src/cpu/o3/rename.hh 3c38d3e74980 src/cpu/o3/rename_impl.hh 3c38d3e74980 src/cpu/o3/rename_map.hh 3c38d3e74980 src/cpu/o3/rename_map.cc 3c38d3e74980 src/cpu/o3/thread_context.hh 3c38d3e74980 src/cpu/o3/thread_context_impl.hh 3c38d3e74980 src/cpu/reg_class.hh 3c38d3e74980 src/cpu/reg_class.cc 3c38d3e74980 src/cpu/reg_class_impl.hh PRE-CREATION src/cpu/simple/base.cc 3c38d3e74980 src/cpu/simple/exec_context.hh 3c38d3e74980 src/cpu/simple_thread.hh 3c38d3e74980 src/cpu/static_inst.hh 3c38d3e74980 src/cpu/thread_context.hh 3c38d3e74980 src/cpu/thread_context.cc 3c38d3e74980 src/sim/serialize.cc 3c38d3e74980 Diff: http://reviews.gem5.org/r/3758/diff/ Testing ------- Builtin regressions Thanks, Rekai Gonzalez Alberquilla _______________________________________________ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
